Searched refs:LWR (Results 1 – 18 of 18) sorted by relevance
| /external/v8/src/mips/ |
| D | constants-mips.cc | 317 case LWR: in InstructionType()
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| D | constants-mips.h | 350 LWR = ((4 << 3) + 6) << kOpcodeShift, enumerator
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| D | disasm-mips.cc | 1187 case LWR: in DecodeTypeImmediate()
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| D | simulator-mips.cc | 2876 case LWR: { in DecodeTypeImmediate()
2969 case LWR: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 1722 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
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| /external/v8/src/mips64/ |
| D | constants-mips64.cc | 337 case LWR: in InstructionType()
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| D | constants-mips64.h | 319 LWR = ((4 << 3) + 6) << kOpcodeShift, enumerator
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| D | disasm-mips64.cc | 1330 case LWR: in DecodeTypeImmediate()
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| D | simulator-mips64.cc | 3023 case LWR: { in DecodeTypeImmediate()
3122 case LWR: in DecodeTypeImmediate()
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| D | assembler-mips64.cc | 1859 GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); in lwr()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 222 case Mips::LWR: in isBasePlusOffsetMemoryAccess()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.h | 199 LWR, enumerator
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| D | MipsISelLowering.cpp | 149 case MipsISD::LWR: return "MipsISD::LWR"; in getTargetNodeName()
2170 SDValue LWR = createLoadLR(MipsISD::LWR, DAG, LD, LWL.getValue(1), LWL, in lowerLOAD() local
2182 return LWR; in lowerLOAD()
2195 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); in lowerLOAD()
2197 SDValue Ops[] = { SRL, LWR.getValue(1) }; in lowerLOAD()
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| D | MipsInstrInfo.td | 131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
1211 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
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| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-BE | 286 LWR
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| D | MIPS32int.stdout.exp-mips32-LE | 286 LWR
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| D | MIPS32int.stdout.exp-mips32r2-LE | 672 LWR
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| D | MIPS32int.stdout.exp-mips32r2-BE | 672 LWR
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