| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCFGOptimizer.cpp | 73 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
76 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
80 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
84 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
88 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
95 MI->setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
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| D | HexagonVLIWPacketizer.cpp | 435 int NewOpcode; in PromoteToDotNew() local
437 NewOpcode = QII->GetDotNewPredOp(MI, MBPI); in PromoteToDotNew()
439 NewOpcode = QII->GetDotNewOp(MI); in PromoteToDotNew()
440 MI->setDesc(QII->get(NewOpcode)); in PromoteToDotNew()
447 int NewOpcode = QII->GetDotOldOp(MI->getOpcode()); in DemoteToDotOld() local
448 MI->setDesc(QII->get(NewOpcode)); in DemoteToDotOld()
762 int NewOpcode = QII->GetDotNewOp(MI); in CanPromoteToDotNew() local
763 const MCInstrDesc &desc = QII->get(NewOpcode); in CanPromoteToDotNew()
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| D | HexagonInstrInfo.cpp | 1655 int NewOpcode = Hexagon::getPredNewOpcode(MI->getOpcode()); in GetDotNewPredOp() local
1656 if (NewOpcode >= 0) // Valid predicate new instruction in GetDotNewPredOp()
1657 return NewOpcode; in GetDotNewPredOp()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 138 int NewOpcode; in InsertSPImmInst() local
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
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| /external/llvm/lib/Target/R600/ |
| D | AMDILCFGStructurizer.cpp | 231 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
233 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
235 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
236 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
239 MachineBasicBlock::iterator I, int NewOpcode, int RegNum,
241 void insertCondBranchEnd(MachineBasicBlock *MBB, int NewOpcode, int RegNum);
472 int NewOpcode, DebugLoc DL) { in insertInstrEnd() argument
474 ->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
481 int NewOpcode, DebugLoc DL) { in insertInstrBefore() argument
483 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
[all …]
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| D | SIInstrInfo.cpp | 2009 unsigned NewOpcode = getVALUOp(*MI); in moveSMRDToVALU() local
2060 MI->setDesc(get(NewOpcode)); in moveSMRDToVALU()
2073 RI.getRegClass(get(NewOpcode).OpInfo[0].RegClass); in moveSMRDToVALU()
2114 unsigned NewOpcode = getVALUOp(*Inst); in moveToVALU() local
2180 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALU()
2186 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALU()
2192 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; in moveToVALU()
2198 NewOpcode = AMDGPU::V_LSHLREV_B64; in moveToVALU()
2204 NewOpcode = AMDGPU::V_ASHRREV_I64; in moveToVALU()
2210 NewOpcode = AMDGPU::V_LSHRREV_B64; in moveToVALU()
[all …]
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| D | SIISelLowering.cpp | 1966 unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet); in AdjustInstrPostInstrSelection() local
1967 MI->setDesc(TII->get(NewOpcode)); in AdjustInstrPostInstrSelection()
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 51 unsigned NewOpcode) const { in splitMove()
73 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
74 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
91 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
92 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
93 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
725 unsigned NewOpcode; in convertToThreeAddress() local
727 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
730 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
732 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
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| D | SystemZFrameLowering.cpp | 429 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
433 if (!NewOpcode) { in emitEpilogue()
438 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
439 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
442 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
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| D | SystemZInstrInfo.h | 121 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 4014 unsigned NewOpcode; in PeepholePPC64ZExt() local
4018 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break; in PeepholePPC64ZExt()
4019 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
4020 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
4021 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
4022 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
4023 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
4024 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
4025 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break; in PeepholePPC64ZExt()
4026 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break; in PeepholePPC64ZExt()
[all …]
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| D | PPCAsmPrinter.cpp | 937 unsigned NewOpcode = in EmitInstruction() local
941 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
951 unsigned NewOpcode = in EmitInstruction() local
957 EmitToStreamer(OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
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| D | PPCRegisterInfo.cpp | 851 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
852 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 179 int NewOpcode = Mips::Std2MicroMips (Opcode, Mips::Arch_micromips); in EncodeInstruction() local
180 if (NewOpcode != -1) { in EncodeInstruction()
183 Opcode = NewOpcode; in EncodeInstruction()
184 TmpInst.setOpcode (NewOpcode); in EncodeInstruction()
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| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| D | PPCAsmParser.cpp | 1559 std::string NewOpcode; in ParseInstruction() local
1562 NewOpcode = Name; in ParseInstruction()
1563 NewOpcode += '+'; in ParseInstruction()
1564 Name = NewOpcode; in ParseInstruction()
1568 NewOpcode = Name; in ParseInstruction()
1569 NewOpcode += '-'; in ParseInstruction()
1570 Name = NewOpcode; in ParseInstruction()
1576 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1584 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
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| /external/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 316 unsigned NewOpcode = 0; in SimplifyMOVSX() local
323 NewOpcode = X86::CBW; in SimplifyMOVSX()
327 NewOpcode = X86::CWDE; in SimplifyMOVSX()
331 NewOpcode = X86::CDQE; in SimplifyMOVSX()
335 if (NewOpcode != 0) { in SimplifyMOVSX()
337 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
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| D | X86InstrInfo.cpp | 4279 unsigned NewOpcode = 0; in optimizeCompareInstr() local
4302 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; in optimizeCompareInstr()
4303 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; in optimizeCompareInstr()
4304 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; in optimizeCompareInstr()
4305 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; in optimizeCompareInstr()
4306 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; in optimizeCompareInstr()
4307 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; in optimizeCompareInstr()
4308 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; in optimizeCompareInstr()
4309 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break; in optimizeCompareInstr()
4310 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break; in optimizeCompareInstr()
[all …]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 506 unsigned NewOpcode = in replaceWithCompactBranch() local
510 const MCInstrDesc &NewDesc = TII->get(NewOpcode); in replaceWithCompactBranch()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 2116 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; in expandLoadStoreMultiple() local
2127 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; in expandLoadStoreMultiple()
2129 Inst.setOpcode(NewOpcode); in expandLoadStoreMultiple()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3943 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
3947 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()
3955 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; in visitXOR() local
3959 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); in visitXOR()
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