Searched refs:OpEntry (Results 1 – 2 of 2) sorted by relevance
748 SDValue &OpEntry = PromotedIntegers[Op]; in SetPromotedInteger() local749 assert(!OpEntry.getNode() && "Node is already promoted!"); in SetPromotedInteger()750 OpEntry = Result; in SetPromotedInteger()759 SDValue &OpEntry = SoftenedFloats[Op]; in SetSoftenedFloat() local760 assert(!OpEntry.getNode() && "Node is already converted to integer!"); in SetSoftenedFloat()761 OpEntry = Result; in SetSoftenedFloat()770 SDValue &OpEntry = PromotedFloats[Op]; in SetPromotedFloat() local771 assert(!OpEntry.getNode() && "Node is already promoted!"); in SetPromotedFloat()772 OpEntry = Result; in SetPromotedFloat()784 SDValue &OpEntry = ScalarizedVectors[Op]; in SetScalarizedVector() local[all …]
1659 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local1669 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()1671 if (OpEntry.OpSignExtend) { in X86SelectDivRem()1672 if (OpEntry.IsOpSigned) in X86SelectDivRem()1674 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()1700 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()1712 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()1730 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()