Searched refs:ShiftBits (Results 1 – 4 of 4) sorted by relevance
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCRegisterInfo.cpp | 513 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore() local
516 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
600 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore() local
604 .addImm(ShiftBits ? 32-ShiftBits : 0) in lowerCRBitRestore()
605 .addImm(ShiftBits).addImm(ShiftBits); in lowerCRBitRestore()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1699 unsigned ShiftBits = AndRHSC.countTrailingZeros(); in SimplifySetCC() local
1704 DAG.getConstant(ShiftBits, ShiftTy)); in SimplifySetCC()
1705 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), CmpTy); in SimplifySetCC()
1716 unsigned ShiftBits; in SimplifySetCC() local
1720 ShiftBits = C1.countTrailingOnes(); in SimplifySetCC()
1724 ShiftBits = C1.countTrailingZeros(); in SimplifySetCC()
1726 NewC = NewC.lshr(ShiftBits); in SimplifySetCC()
1727 if (ShiftBits && isLegalICmpImmediate(NewC.getSExtValue())) { in SimplifySetCC()
1732 DAG.getConstant(ShiftBits, ShiftTy)); in SimplifySetCC()
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| /external/llvm/lib/Analysis/ |
| D | BasicAliasAnalysis.cpp | 401 if (unsigned ShiftBits = 64 - DL.getPointerSizeInBits(AS)) { in DecomposeGEPExpression() local
402 Scale <<= ShiftBits; in DecomposeGEPExpression()
403 Scale = (int64_t)Scale >> ShiftBits; in DecomposeGEPExpression()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 6008 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8); in LowerCONCAT_VECTORSvXi1() local
6011 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits); in LowerCONCAT_VECTORSvXi1()
6017 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits); in LowerCONCAT_VECTORSvXi1()
6018 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits); in LowerCONCAT_VECTORSvXi1()
10825 SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8); in LowerINSERT_SUBVECTOR() local
10829 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits); in LowerINSERT_SUBVECTOR()
10830 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits); in LowerINSERT_SUBVECTOR()
10834 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits); in LowerINSERT_SUBVECTOR()
10841 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits); in LowerINSERT_SUBVECTOR()
10842 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits); in LowerINSERT_SUBVECTOR()
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