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Searched refs:WriteI (Results 1 – 7 of 7) sorted by relevance

/external/llvm/lib/CodeGen/
DLiveInterval.cpp1160 OS << " updater with gap = " << (ReadI - WriteI) in print()
1163 for (const auto &S : make_range(LR->begin(), WriteI)) in print()
1207 WriteI = ReadI = LR->begin(); in add()
1217 if (ReadI != WriteI) in add()
1220 if (ReadI == WriteI) in add()
1221 ReadI = WriteI = LR->find(Seg.start); in add()
1224 *WriteI++ = *ReadI++; in add()
1254 if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) { in add()
1255 WriteI[-1].end = std::max(WriteI[-1].end, Seg.end); in add()
1260 if (WriteI != ReadI) { in add()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64SchedA53.td58 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
154 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
158 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
162 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
178 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
182 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
188 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
199 def : InstRW<[WriteI], (instrs COPY)>;
DAArch64SchedA57.td71 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
125 def : InstRW<[WriteI], (instrs COPY)>;
140 SchedVar<NoSchedPred, [WriteI]>]>;
576 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
582 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
589 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
595 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
605 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
DAArch64Schedule.td25 def WriteI : SchedWrite; // ALU
DAArch64SchedCyclone.td124 SchedVar<NoSchedPred, [WriteI]>]>;
148 def : WriteRes<WriteI, [CyUnitI]>;
290 def : InstRW<[WriteI], (instrs ISB)>;
357 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
DAArch64InstrFormats.td1177 Sched<[WriteI, ReadI]> {
1216 Sched<[WriteI, ReadI, ReadI]> {
1433 Sched<[WriteI]> {
1497 Sched<[WriteI, ReadI]> {
1530 Sched<[WriteI, ReadI]> {
1548 Sched<[WriteI, ReadI, ReadI]>;
1920 Sched<[WriteI, ReadI]> {
2016 Sched<[WriteI, ReadI, ReadI]>;
2074 Sched<[WriteI, ReadI]> {
2106 Sched<[WriteI, ReadI, ReadI]> {
[all …]
/external/llvm/include/llvm/CodeGen/
DLiveInterval.h780 LiveRange::iterator WriteI; variable