Searched refs:createQuadDRegsNode (Results 1 – 1 of 1) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 271 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1621 SDNode *ARMDAGToDAGISel::createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, in createQuadDRegsNode() function in ARMDAGToDAGISel
1973 SrcReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVST()
2140 SuperReg = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVLDSTLane()
2274 RegSeq = SDValue(createQuadDRegsNode(MVT::v4i64, V0, V1, V2, V3), 0); in SelectVTBL()
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