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Searched refs:decw (Results 1 – 22 of 22) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dmisched-aa-mmos.ll3 ; This generates a decw instruction, which has two MMOs, and an alias SU edge
Dlsr-wrap.ll7 ; CHECK: decw %
Datomic_add.ll178 ; CHECK: decw
180 ; SLOW_INC-NOT: decw
Datomic16.ll41 ; X64: decw
43 ; X32: decw
Datomic_mi.ll471 ; X64-NOT: decw
473 ; X32-NOT: decw
475 ; SLOW_INC-NOT: decw
Drd-mod-wr-eflags.ll97 ; CHECK: decw {{[0-9][0-9]*}}({{.*}})
/external/llvm/test/MC/X86/
Dx86-16.s553 decw %ax
Dx86-32.s643 decw %ax
Dx86-64.s950 decw %ax // CHECK: decw %ax # encoding: [0x66,0xff,0xc8] label
Dx86-32-coverage.s505 decw 0x7eed
/external/llvm/test/MC/Disassembler/X86/
Dx86-64.txt215 # CHECK: decw %cx
Dx86-16.txt510 # CHECK: decw %ax
Dx86-32.txt700 # CHECK: decw %cx
/external/valgrind/none/tests/x86/
Dx86locked.c448 GEN_do_locked_unary_E(decw,ax)
Dinsn_basic.def425 decw r16.uw[12345] => 0.uw[12344]
426 decw m16.uw[12345] => 0.uw[12344]
/external/valgrind/none/tests/amd64/
Damd64locked.c484 GEN_do_locked_unary_E(decw,ax)
Dinsn_basic.def558 decw r16.uw[12345] => 0.uw[12344]
559 decw m16.uw[12345] => 0.uw[12344]
/external/mesa3d/include/GL/
Dvms_x_fix.h15 #define decw$_select DECW$_SELECT
/external/mesa3d/src/mesa/x86/
Dassyntax.h428 #define DEC_W(a) CHOICE(decw a, decw a, _WTOG dec a)
/external/valgrind/perf/
Dtinycc.c3287 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
3744 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
4619 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
5076 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
15326 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
15788 ALT(DEF_ASM_OP1(decw, 0x48, 0, OPC_REG | OPC_WL, OPT_REGW))
/external/elfutils/src/tests/
Dtestfile44.expect.bz2
Dtestfile45.expect.bz21testfile45.o: elf64-elf_x86_64 2 3Disassembly of section .text: 4 5 0 ...