| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 9 add.d $f1,$f7,$f29
27 c.ngl.d $f29,$f29
40 div.d $f29,$f20,$f27
|
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/CodeGen/PowerPC/ |
| D | vsx-spill.ll | 10 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
31 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() n…
51 …8},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0…
|
| /external/llvm/test/MC/Mips/mips32r3/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
126 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips32r5/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
126 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips32r2/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
57 cvt.l.s $f11,$f29
66 div.d $f29,$f20,$f27
126 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips32/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
62 div.d $f29,$f20,$f27
111 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips4/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
58 cvt.l.s $f11,$f29
77 div.d $f29,$f20,$f27
164 movz.d $f12,$f29,$9
|
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| /external/llvm/test/MC/Mips/mips5/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
58 cvt.l.s $f11,$f29
77 div.d $f29,$f20,$f27
165 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips2/ |
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | valid.s | 11 add.d $f1,$f7,$f29
39 c.ngl.d $f29,$f29
54 div.d $f29,$f20,$f27
|
| /external/llvm/test/MC/Mips/mips3/ |
| D | invalid-mips5-wrong-error.s | 24 c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
37 msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
43 plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | valid.s | 11 add.d $f1,$f7,$f29
40 c.ngl.d $f29,$f29
54 cvt.l.s $f11,$f29
73 div.d $f29,$f20,$f27
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips5-wrong-error.s | 27 … c.ueq.ps $fcc1,$f5,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
39 … msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
45 … plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction
|
| D | invalid-mips1.s | 14 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/llvm/test/MC/Mips/mips64/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
60 cvt.l.s $f11,$f29
82 div.d $f29,$f20,$f27
175 movz.d $f12,$f29,$9
|
| /external/llvm/test/CodeGen/Mips/ |
| D | no-odd-spreg-msa.ll | 22 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
56 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
86 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
114 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
|
| /external/llvm/test/MC/Mips/mips64r3/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
60 cvt.l.s $f11,$f29
84 div.d $f29,$f20,$f27
191 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips64r5/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
60 cvt.l.s $f11,$f29
84 div.d $f29,$f20,$f27
191 movz.d $f12,$f29,$9
|
| /external/llvm/test/MC/Mips/mips64r2/ |
| D | valid.s | 11 add.d $f1,$f7,$f29
44 c.ngl.d $f29,$f29
60 cvt.l.s $f11,$f29
84 div.d $f29,$f20,$f27
191 movz.d $f12,$f29,$9
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | callee-saved-float.ll | 26 …,~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"()
68 ; O32-INV-NOT: sdc1 $f29,
87 ; N32-INV-NOT: sdc1 $f29,
100 ; N64-DAG: sdc1 [[F29:\$f29]], [[OFF29:[0-9]+]]($sp)
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips1.s | 11 …c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
|
| /external/compiler-rt/lib/builtins/ppc/ |
| D | saveFP.S | 36 stfd f29,-24(r1)
|
| D | restFP.S | 38 lfd f29,-24(r1)
|