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Searched refs:fcvtxn (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/AArch64/
Darm64-vcvtxd_f32_f64.ll3 define float @fcvtxn(double %a) {
4 ; CHECK-LABEL: fcvtxn:
5 ; CHECK: fcvtxn s0, d0
7 %vcvtxd.i = tail call float @llvm.aarch64.sisd.fcvtxn(double %a) nounwind
11 declare float @llvm.aarch64.sisd.fcvtxn(double) nounwind readnone
Darm64-vcvt_f.ll41 %vcvtx1.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
42 ; CHECK: fcvtxn
49 %vcvtx2.i = tail call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %v) nounwind
63 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
Darm64-vcvt.ll526 ;CHECK: fcvtxn v0.2s, v0.2d
528 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
537 %tmp3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)
542 declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone
/external/llvm/test/MC/AArch64/
Dneon-scalar-cvt.s70 fcvtxn s22, d13
Dneon-simd-misc.s430 fcvtxn v4.2s, v0.2d
Dneon-diagnostics.s5820 fcvtxn v6.4s, v8.2d
7166 fcvtxn s0, s1
Darm64-advsimd.s715 fcvtxn v6.2s, v9.2d
722 ; CHECK: fcvtxn v6.2s, v9.2d ; encoding: [0x26,0x69,0x61,0x2e]
/external/vixl/test/
Dtest-simulator-a64.cc3968 DEFINE_TEST_NEON_2DIFF_FP_NARROW_2S(fcvtxn, Conversions) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
4015 CALL_TEST_NEON_HELPER_2DIFF(fcvtxn, S, D, kInputDoubleConversions); in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
/external/vixl/src/vixl/a64/
Dsimulator-a64.cc2559 fcvtxn(vf_fcvtn, rd, rn); in VisitNEON2RegMisc()
3510 fcvtxn(kFormatS, rd, rn); in VisitNEONScalar2RegMisc()
Dsimulator-a64.h2464 LogicVRegister fcvtxn(VectorFormat vform,
Dmacro-assembler-a64.h1211 fcvtxn(vd, vn); in Fcvtxn()
Dassembler-a64.h2105 void fcvtxn(const VRegister& vd, const VRegister& vn);
Dlogic-a64.cc4496 LogicVRegister Simulator::fcvtxn(VectorFormat vform, in fcvtxn() function in vixl::Simulator
Dassembler-a64.cc2805 void Assembler::fcvtxn(const VRegister& vd, in fcvtxn() function in vixl::Assembler
/external/vixl/doc/
Dsupported-instructions.md1990 void fcvtxn(const VRegister& vd, const VRegister& vn)
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt563 # CHECK: fcvtxn v0.2s, v0.2d
Dneon-instructions.txt2535 # CHECK: fcvtxn s22, d13
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td2594 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
3095 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
/external/valgrind/none/tests/arm64/
Dfp_and_simd.stdout.exp26838 fcvtxn s10, d21 6703e8d6cbffa3e96e2088fe0c404ef3 acdc6e6f4bf5a9501d87ee7e4d861e1c 0000000000000…
26839 fcvtxn v10.2s, v21.2d d2dcb2a585e4bade8d3a11f81ddbd8a4 3b2152911c72e8d11d9fc6b5613bb6b1 000000…