| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
105 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
230 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency()
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| D | TargetInstrInfo.cpp | 730 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
733 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
745 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
758 unsigned Class = MI->getDesc().getSchedClass(); in getNumMicroOps()
793 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrLatency()
802 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
813 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
814 unsigned UseClass = UseMI->getDesc().getSchedClass(); in getOperandLatency()
861 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
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| D | DFAPacketizer.cpp | 67 unsigned InsnClass = MID->getSchedClass(); in canReserveResources()
79 unsigned InsnClass = MID->getSchedClass(); in reserveResources()
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| D | ScoreboardHazardRecognizer.cpp | 134 unsigned idx = MCID->getSchedClass(); in getHazardType()
194 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
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| D | MachineCombiner.cpp | 261 unsigned Idx = TII->get(Opc).getSchedClass(); in instr2instrSC()
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| D | MachineScheduler.cpp | 1626 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I); in init()
1707 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
1910 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2135 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
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| D | ScheduleDAGInstrs.cpp | 724 const MCSchedClassDesc *SC = getSchedClass(SU); in initSUnits()
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 169 unsigned SCClass = Desc.getSchedClass(); in getItineraryLatency()
196 unsigned SCClass = Desc.getSchedClass(); in getLatency()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
92 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 340 CodeGenSchedClass &getSchedClass(unsigned Idx) { in getSchedClass() function
344 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { in getSchedClass() function
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| D | SubtargetEmitter.cpp | 588 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; in EmitItineraries()
1142 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" in EmitSchedClassTables()
1150 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1312 const CodeGenSchedClass &SC = SchedModels.getSchedClass(*VCI); in EmitSchedModelHelpers()
1347 << SchedModels.getSchedClass(TI->ToClassIdx).Name << '\n'; in EmitSchedModelHelpers()
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| D | CodeGenSchedule.cpp | 542 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
1321 SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans); in inferFromTransitions()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 81 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 172 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 621 unsigned getSchedClass() const { in getSchedClass() function
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 2727 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
2983 unsigned Class = Desc.getSchedClass(); in getNumMicroOps()
3271 unsigned DefClass = DefMCID.getSchedClass(); in getOperandLatency()
3272 unsigned UseClass = UseMCID.getSchedClass(); in getOperandLatency()
3717 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
3967 unsigned Class = MCID.getSchedClass(); in getInstrLatency()
3997 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency()
4034 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
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| D | ARMISelLowering.cpp | 1206 Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) in getSchedulingPreference()
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| /external/llvm/lib/Target/R600/ |
| D | R600InstrInfo.cpp | 182 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU); in isTransOnly()
190 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU); in isVectorOnly()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonVLIWPacketizer.cpp | 960 unsigned SchedClass = TID.getSchedClass(); in ignorePseudoInstruction()
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| /external/llvm/docs/ |
| D | WritingAnLLVMBackend.rst | 1012 Instruction itineraries can be queried using MCDesc::getSchedClass(). The
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