| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| D | nv50_ir_build_util.cpp | 47 memset(imms, 0, sizeof(imms)); in init()
59 while (imms[pos]) in addImmediate()
61 imms[pos] = imm; in addImmediate()
358 while (imms[pos] && imms[pos]->reg.data.u32 != u) in mkImm()
361 ImmediateValue *imm = imms[pos]; in mkImm()
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| D | nv50_ir_build_util.h | 182 ImmediateValue *imms[NV50_IR_BUILD_IMM_HT_SIZE]; variable
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| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 296 unsigned imms = val & 0x3f; in decodeLogicalImmediate() local
299 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in decodeLogicalImmediate()
303 unsigned S = imms & (size - 1); in decodeLogicalImmediate()
324 unsigned imms = val & 0x3f; in isValidDecodeLogicalImmediate() local
328 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f)); in isValidDecodeLogicalImmediate()
332 unsigned S = imms & (size - 1); in isValidDecodeLogicalImmediate()
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| /external/mesa3d/src/gallium/auxiliary/translate/ |
| D | translate_sse.c | 455 unsigned imms[2] = {0, 0x3f800000}; in translate_attr_convert() local
658 x86_mov_imm(p->func, dst, imms[swizzle[0] - UTIL_FORMAT_SWIZZLE_0]); in translate_attr_convert()
668 … x86_mov_imm(p->func, x86_make_disp(dst, 4), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]); in translate_attr_convert()
686 … x86_mov_imm(p->func, x86_make_disp(dst, 8), imms[swizzle[2] - UTIL_FORMAT_SWIZZLE_0]); in translate_attr_convert()
696 … x86_mov_imm(p->func, x86_make_disp(dst, 12), imms[swizzle[3] - UTIL_FORMAT_SWIZZLE_0]); in translate_attr_convert()
714 unsigned imms[2] = {0, 1}; in translate_attr_convert() local
773 … imms[1] = (output_desc->channel[0].type == UTIL_FORMAT_TYPE_UNSIGNED) ? 0xffff : 0x7ffff; in translate_attr_convert()
797 … x86_mov16_imm(p->func, x86_make_disp(dst, 2), imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0]); in translate_attr_convert()
803 …x86_mov_imm(p->func, dst, (imms[swizzle[1] - UTIL_FORMAT_SWIZZLE_0] << 16) | imms[swizzle[0] - UTI… in translate_attr_convert()
806 x86_mov16_imm(p->func, dst, imms[swizzle[0] - UTIL_FORMAT_SWIZZLE_0]); in translate_attr_convert()
[all …]
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 113 int64_t imms = Op3.getImm(); in printInst() local
114 if (Opcode == AArch64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) { in printInst()
116 shift = 31 - imms; in printInst()
117 } else if (Opcode == AArch64::UBFMXri && imms != 0x3f && in printInst()
118 ((imms + 1 == immr))) { in printInst()
120 shift = 63 - imms; in printInst()
121 } else if (Opcode == AArch64::UBFMWri && imms == 0x1f) { in printInst()
124 } else if (Opcode == AArch64::UBFMXri && imms == 0x3f) { in printInst()
127 } else if (Opcode == AArch64::SBFMWri && imms == 0x1f) { in printInst()
130 } else if (Opcode == AArch64::SBFMXri && imms == 0x3f) { in printInst()
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 1067 Instr Assembler::ImmS(unsigned imms, unsigned reg_size) {
1068 DCHECK(((reg_size == kXRegSizeInBits) && is_uint6(imms)) ||
1069 ((reg_size == kWRegSizeInBits) && is_uint5(imms)));
1071 return imms << ImmS_offset;
1084 Instr Assembler::ImmSetBits(unsigned imms, unsigned reg_size) {
1086 DCHECK(is_uint6(imms));
1087 DCHECK((reg_size == kXRegSizeInBits) || is_uint6(imms + 3));
1089 return imms << ImmSetBits_offset;
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| D | assembler-arm64.h | 1200 unsigned imms);
1206 unsigned imms);
1212 unsigned imms);
1821 inline static Instr ImmS(unsigned imms, unsigned reg_size);
1823 inline static Instr ImmSetBits(unsigned imms, unsigned reg_size);
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| D | assembler-arm64.cc | 1280 unsigned imms) { in bfm() argument
1285 ImmS(imms, rn.SizeInBits()) | in bfm()
1293 unsigned imms) { in sbfm() argument
1298 ImmS(imms, rn.SizeInBits()) | in sbfm()
1306 unsigned imms) { in ubfm() argument
1311 ImmS(imms, rn.SizeInBits()) | in ubfm()
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-basic-a64-undefined.txt | 20 # UBFM is undefined when s == 0 and imms<5> or immr<5> is 1.
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| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 1344 unsigned imms);
1350 unsigned imms);
1356 unsigned imms);
3806 static Instr ImmS(unsigned imms, unsigned reg_size) { in ImmS() argument
3807 VIXL_ASSERT(((reg_size == kXRegSize) && is_uint6(imms)) || in ImmS()
3808 ((reg_size == kWRegSize) && is_uint5(imms))); in ImmS()
3810 return imms << ImmS_offset; in ImmS()
3821 static Instr ImmSetBits(unsigned imms, unsigned reg_size) { in ImmSetBits() argument
3823 VIXL_ASSERT(is_uint6(imms)); in ImmSetBits()
3824 VIXL_ASSERT((reg_size == kXRegSize) || is_uint6(imms + 3)); in ImmSetBits()
[all …]
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| D | macro-assembler-a64.h | 978 unsigned imms) { in Bfm() argument
983 bfm(rd, rn, immr, imms); in Bfm()
1708 unsigned imms) { in Sbfm() argument
1713 sbfm(rd, rn, immr, imms); in Sbfm()
1974 unsigned imms) { in Ubfm() argument
1979 ubfm(rd, rn, immr, imms); in Ubfm()
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| D | assembler-a64.cc | 1058 unsigned imms) { in bfm() argument
1062 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in bfm()
1069 unsigned imms) { in sbfm() argument
1073 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in sbfm()
1080 unsigned imms) { in ubfm() argument
1084 ImmR(immr, rd.size()) | ImmS(imms, rn.size()) | Rn(rn) | Rd(rd)); in ubfm()
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| /external/sepolicy/ |
| D | service_contexts | 54 imms u:object_r:imms_service:s0
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| /external/vixl/doc/ |
| D | supported-instructions.md | 153 unsigned imms)
1024 unsigned imms)
1337 unsigned imms)
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 1846 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1847 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1852 bits<6> imms;
1857 let Inst{15-10} = imms;
1866 // imms<5> and immr<5> must be zero, else ReservedValue().
1880 imm_type:$imms),
1881 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1886 bits<6> imms;
1891 let Inst{15-10} = imms;
1900 // imms<5> and immr<5> must be zero, else ReservedValue().
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| /external/elfutils/src/libcpu/defs/ |
| D | i386 | 30 %mask {imms} 8
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| /external/valgrind/VEX/priv/ |
| D | guest_arm64_toIR.c | 2329 ULong immN, ULong imms, ULong immr, Bool immediate, in dbm_DecodeBitMasks() argument
2333 vassert(imms < (1ULL << 6)); in dbm_DecodeBitMasks()
2338 Int len = dbm_highestSetBit( ((immN << 6) & 64) | ((~imms) & 63) ); in dbm_DecodeBitMasks()
2348 if (immediate && ((imms & levels) == levels)) { in dbm_DecodeBitMasks()
2353 ULong S = imms & levels; in dbm_DecodeBitMasks()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 1448 // Two piece imms.
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 1494 // Helper imms that check if a mask doesn't change significant shift bits.
|