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Searched refs:lane_size (Results 1 – 3 of 3) sorted by relevance

/external/vixl/src/vixl/a64/
Dassembler-a64.cc2260 unsigned lane_size = vt.LaneSizeInBytes(); in LoadStoreStructSingle() local
2261 VIXL_ASSERT(lane < (kQRegSizeInBytes / lane_size)); in LoadStoreStructSingle()
2265 lane *= lane_size; in LoadStoreStructSingle()
2266 if (lane_size == 8) lane++; in LoadStoreStructSingle()
2273 switch (lane_size) { in LoadStoreStructSingle()
2278 VIXL_ASSERT(lane_size == 8); in LoadStoreStructSingle()
3714 int lane_size = vn.LaneSizeInBytes(); in dup() local
3716 switch (lane_size) { in dup()
3721 VIXL_ASSERT(lane_size == 8); in dup()
3762 int lane_size = vd.LaneSizeInBytes(); in ins() local
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Dsimulator-a64.cc428 unsigned reg_size, unsigned lane_size) { in GetPrintRegisterFormatForSize() argument
429 VIXL_ASSERT(reg_size >= lane_size); in GetPrintRegisterFormatForSize()
432 if (reg_size != lane_size) { in GetPrintRegisterFormatForSize()
440 switch (lane_size) { in GetPrintRegisterFormatForSize()
698 int lane_size = 1 << lane_size_log2; in PrintVRegister() local
709 PrintVRegisterFPHelper(code, lane_size, lane_count); in PrintVRegister()
803 int lane_size = GetPrintRegLaneSizeInBytes(format); in PrintVWrite() local
805 PrintVRegisterRawHelper(reg_code, reg_size, lane_size * lane); in PrintVWrite()
807 PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane); in PrintVWrite()
3103 int lane_size = LaneSizeInBytesFromFormat(vf); in NEONLoadStoreMultiStructHelper() local
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Dsimulator-a64.h1178 unsigned lane_size);