| /external/llvm/test/MC/AArch64/ |
| D | arm64-memory.s | 284 ldpsw x2, x3, [x14, #16]
285 ldpsw x2, x3, [sp, #-16]
292 ; CHECK: ldpsw x2, x3, [x14, #16] ; encoding: [0xc2,0x0d,0x42,0x69]
293 ; CHECK: ldpsw x2, x3, [sp, #-16] ; encoding: [0xe2,0x0f,0x7e,0x69]
316 ldpsw x2, x3, [x14, #16]!
317 ldpsw x2, x3, [sp, #-16]!
323 ; CHECK: ldpsw x2, x3, [x14, #16]! ; encoding: [0xc2,0x0d,0xc2,0x69]
324 ; CHECK: ldpsw x2, x3, [sp, #-16]! ; encoding: [0xe2,0x0f,0xfe,0x69]
344 ldpsw x2, x3, [x14], #16
345 ldpsw x2, x3, [sp], #-16
[all …]
|
| D | basic-a64-diagnostics.s | 2522 ldpsw x9, x2, [sp, #2]
2523 ldpsw x1, x2, [x10, #256]
2524 ldpsw x3, x4, [x11, #-260]
2625 ldpsw x9, x2, [sp], #2
2626 ldpsw x1, x2, [x10], #256
2627 ldpsw x3, x4, [x11], #-260
2728 ldpsw x9, x2, [sp, #2]!
2729 ldpsw x1, x2, [x10, #256]!
2730 ldpsw x3, x4, [x11, #-260]!
|
| D | basic-a64-instructions.s | 2997 ldpsw x9, x10, [sp, #4]
2998 ldpsw x9, x10, [x2, #-256]
2999 ldpsw x20, x30, [sp, #252]
3045 ldpsw x9, x10, [sp], #4
3046 ldpsw x9, x10, [x2], #-256
3047 ldpsw x20, x30, [sp], #252
3092 ldpsw x9, x10, [sp, #4]!
3093 ldpsw x9, x10, [x2, #-256]!
3094 ldpsw x20, x30, [sp, #252]!
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-memory.txt | 290 # CHECK: ldpsw x2, x3, [x14, #16]
291 # CHECK: ldpsw x2, x3, [sp, #-16]
318 # CHECK: ldpsw x2, x3, [x14, #16]!
319 # CHECK: ldpsw x2, x3, [sp, #-16]!
346 # CHECK: ldpsw x2, x3, [x14], #16
347 # CHECK: ldpsw x2, x3, [sp], #-16
|
| D | basic-a64-instructions.txt | 2550 # CHECK: ldpsw x9, x10, [sp, #4]
2551 # CHECK: ldpsw x9, x10, [x2, #-256]
2552 # CHECK: ldpsw x20, x30, [sp, #252]
2598 # CHECK: ldpsw x9, x10, [sp], #4
2599 # CHECK: ldpsw x9, x10, [x2], #-256
2600 # CHECK: ldpsw x20, x30, [sp], #252
2646 # CHECK: ldpsw x9, x10, [sp, #4]!
2647 # CHECK: ldpsw x9, x10, [x2, #-256]!
2648 # CHECK: ldpsw x20, x30, [sp, #252]!
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-ldp.ll | 16 ; CHECK: ldpsw
100 ; LDUR_CHK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-8]
203 ; LDUR_CHK: ldpsw [[DST1:x[0-9]+]], [[DST2:x[0-9]+]], [x0, #-256]
|
| /external/v8/test/cctest/ |
| D | test-disasm-arm64.cc | 1240 COMPARE(ldpsw(x0, x1, MemOperand(x2)), "ldpsw x0, x1, [x2]"); in TEST_()
1241 COMPARE(ldpsw(x3, x4, MemOperand(x5, 16)), "ldpsw x3, x4, [x5, #16]"); in TEST_()
1242 COMPARE(ldpsw(x6, x7, MemOperand(x8, -32, PreIndex)), in TEST_()
1244 COMPARE(ldpsw(x9, x10, MemOperand(x11, 128, PostIndex)), in TEST_()
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1490 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
|
| D | assembler-arm64.cc | 1590 void Assembler::ldpsw(const Register& rt, in ldpsw() function in v8::internal::Assembler
|
| /external/vixl/test/ |
| D | test-disasm-a64.cc | 1719 COMPARE(ldpsw(x0, x1, MemOperand(x2)), "ldpsw x0, x1, [x2]"); in TEST()
1720 COMPARE(ldpsw(x3, x4, MemOperand(x5, 16)), "ldpsw x3, x4, [x5, #16]"); in TEST()
1721 COMPARE(ldpsw(x6, x7, MemOperand(x8, -32, PreIndex)), in TEST()
1723 COMPARE(ldpsw(x9, x10, MemOperand(x11, 128, PostIndex)), in TEST()
|
| D | test-assembler-a64.cc | 15352 __ ldpsw(x2, x3, MemOperand(x0, offset)); in TEST() local
15506 __ ldpsw(x2, x3, MemOperand(x0, preindex, PreIndex)); in TEST() local
15632 __ ldpsw(x2, x3, MemOperand(x0, postindex, PostIndex)); in TEST() local
|
| /external/vixl/src/vixl/a64/ |
| D | assembler-a64.h | 1739 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
|
| D | assembler-a64.cc | 1429 void Assembler::ldpsw(const Register& rt, in ldpsw() function in vixl::Assembler
|
| /external/vixl/doc/ |
| D | supported-instructions.md | 591 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1142 defm LDPSW : LoadPairOffset<0b01, 0, GPR64, simm7s4, "ldpsw">;
1151 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1160 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
|