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Searched refs:load1 (Results 1 – 25 of 29) sorted by relevance

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/external/llvm/test/Transforms/SLPVectorizer/X86/
Dpropagate_ir_flags.ll18 %load1 = load i32, i32* %idx1, align 4
23 %op1 = lshr exact i32 %load1, 1
44 %load1 = load i32, i32* %idx1, align 4
49 %op1 = lshr exact i32 %load1, 1
70 %load1 = load i32, i32* %idx1, align 4
75 %op1 = add nsw i32 %load1, 1
96 %load1 = load i32, i32* %idx1, align 4
101 %op1 = add nsw i32 %load1, 1
122 %load1 = load i32, i32* %idx1, align 4
127 %op1 = add nuw i32 %load1, 1
[all …]
/external/llvm/test/Transforms/LoadCombine/
Dload-combine-aa.ll11 %load1 = load i32, i32* %a, align 4
12 %conv = zext i32 %load1 to i64
14 store i32 %load1, i32* %b, align 4
29 %load1 = load i32, i32* %a, align 4
30 %conv = zext i32 %load1 to i64
32 store i32 %load1, i32* %b, align 4
Dload-combine-assume.ll15 %load1 = load i32, i32* %a, align 4
16 %conv = zext i32 %load1 to i64
34 %load1 = load i32, i32* %a, align 4
35 %conv = zext i32 %load1 to i64
/external/libvpx/libvpx/vp9/common/mips/dspr2/
Dvp9_itrans32_dspr2.c39 int load1, load2, load3, load4; in idct32_rows_dspr2() local
152 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
214 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
276 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
338 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
400 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
462 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
664 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
730 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct32_rows_dspr2()
Dvp9_itrans32_cols_dspr2.c38 int load1, load2, load3, load4; in vp9_idct32_cols_add_blk_dspr2() local
109 : [load1] "=&r" (load1), [load2] "=&r" (load2), [load3] "=&r" (load3), in vp9_idct32_cols_add_blk_dspr2()
170 : [load1] "=&r" (load1), [load2] "=&r" (load2), [load3] "=&r" (load3), in vp9_idct32_cols_add_blk_dspr2()
231 : [load1] "=&r" (load1), [load2] "=&r" (load2), [load3] "=&r" (load3), in vp9_idct32_cols_add_blk_dspr2()
288 : [load1] "=&r" (load1), [load2] "=&r" (load2), [load3] "=&r" (load3), in vp9_idct32_cols_add_blk_dspr2()
345 : [load1] "=&r" (load1), [load2] "=&r" (load2), [load3] "=&r" (load3), in vp9_idct32_cols_add_blk_dspr2()
402 : [load1] "=&r" (load1), [load2] "=&r" (load2), [load3] "=&r" (load3), in vp9_idct32_cols_add_blk_dspr2()
596 : [load1] "=&r" (load1), [load2] "=&r" (load2), in vp9_idct32_cols_add_blk_dspr2()
657 : [load1] "=&r" (load1), [load2] "=&r" (load2), in vp9_idct32_cols_add_blk_dspr2()
Dvp9_convolve2_avg_dspr2.c35 uint32_t load1, load2; in convolve_bi_avg_vert_4_dspr2() local
110 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_bi_avg_vert_4_dspr2()
139 uint32_t load1, load2; in convolve_bi_avg_vert_64_dspr2() local
215 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_bi_avg_vert_64_dspr2()
Dvp9_convolve2_vert_dspr2.c35 uint32_t load1, load2; in convolve_bi_vert_4_dspr2() local
103 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_bi_vert_4_dspr2()
132 uint32_t load1, load2; in convolve_bi_vert_64_dspr2() local
200 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_bi_vert_64_dspr2()
Dvp9_convolve8_vert_dspr2.c35 uint32_t load1, load2, load3, load4; in convolve_vert_4_dspr2() local
157 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_vert_4_dspr2()
189 uint32_t load1, load2, load3, load4; in convolve_vert_64_dspr2() local
312 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_vert_64_dspr2()
Dvp9_convolve8_avg_dspr2.c35 uint32_t load1, load2, load3, load4; in convolve_avg_vert_4_dspr2() local
165 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_avg_vert_4_dspr2()
196 uint32_t load1, load2, load3, load4; in convolve_avg_vert_64_dspr2() local
327 : [load1] "=&r" (load1), [load2] "=&r" (load2), in convolve_avg_vert_64_dspr2()
Dvp9_itrans16_dspr2.c30 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_rows_dspr2() local
72 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct16_rows_dspr2()
196 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct16_rows_dspr2()
416 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_cols_add_blk_dspr2() local
468 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct16_cols_add_blk_dspr2()
592 : [load1] "=&r" (load1), [load2] "=&r" (load2), in idct16_cols_add_blk_dspr2()
/external/llvm/test/CodeGen/X86/
Daddr-mode-matcher.ll24 ; %load1 = (load (and (shl %xor, 2), 1020))
29 %load1 = load i32, i32* %tmp1704, align 4
40 ; While matching xor we address-match %load1. The and-of-shift reassocication
42 ; node becomes identical to %load2. CSE replaces %load1 which leaves its
44 %tmp1711 = xor i32 %load1, %tmp1710
/external/llvm/test/CodeGen/AArch64/
Dldst-opt.ll189 %load1 = load %pre.struct.i32*, %pre.struct.i32** %this
190 %gep1 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load1, i64 0, i32 1
207 %load1 = load %pre.struct.i64*, %pre.struct.i64** %this
208 %gep1 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load1, i64 0, i32 1
225 %load1 = load %pre.struct.i128*, %pre.struct.i128** %this
226 %gep1 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load1, i64 0, i32 1
243 %load1 = load %pre.struct.float*, %pre.struct.float** %this
244 %gep1 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load1, i64 0, i32 1
261 %load1 = load %pre.struct.double*, %pre.struct.double** %this
262 %gep1 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load1, i64 0, i32 1
[all …]
Darm64-vabs.ll37 %load1 = load <16 x i8>, <16 x i8>* %A
39 …%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
49 %load1 = load <8 x i16>, <8 x i16>* %A
51 … %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
61 %load1 = load <4 x i32>, <4 x i32>* %A
63 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
103 %load1 = load <16 x i8>, <16 x i8>* %A
105 …%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
116 %load1 = load <8 x i16>, <8 x i16>* %A
118 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
Darm64-vmul.ll87 %load1 = load <8 x i16>, <8 x i16>* %A
89 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
98 %load1 = load <4 x i32>, <4 x i32>* %A
100 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
328 %load1 = load <8 x i16>, <8 x i16>* %A
331 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
341 %load1 = load <4 x i32>, <4 x i32>* %A
344 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
376 %load1 = load <8 x i16>, <8 x i16>* %A
379 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
Df16-convert.ll14 define double @load1(i16* nocapture readonly %a) nounwind {
15 ; CHECK-LABEL: load1:
Darm64-vshift.ll1168 %load1 = load <16 x i8>, <16 x i8>* %A
1169 …%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
1178 %load1 = load <8 x i16>, <8 x i16>* %A
1179 … %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
1188 %load1 = load <4 x i32>, <4 x i32>* %A
1189 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
1225 %load1 = load <16 x i8>, <16 x i8>* %A
1226 …%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
1235 %load1 = load <8 x i16>, <8 x i16>* %A
1236 … %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
/external/llvm/test/CodeGen/R600/
Dschedule-global-loads.ll19 %load1 = load i32, i32 addrspace(1)* %gep, align 4
21 store i32 %load1, i32 addrspace(1)* %out1, align 4
/external/llvm/test/CodeGen/PowerPC/
Dload-shift-combine.ll21 …%bf.load1 = load i96, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5…
22 %bf.clear2 = and i96 %bf.load1, 302231454903657293676543
/external/llvm/test/Instrumentation/AddressSanitizer/
Dexperiment.ll7 define void @load1(i8* %p) sanitize_address {
11 ; CHECK-LABEL: define void @load1
Dexperiment-call.ll7 define void @load1(i8* %p) sanitize_address {
11 ; CHECK-LABEL: define void @load1
/external/llvm/test/Analysis/ValueTracking/
Dmemory-dereferenceable.ll21 %load1 = load i8, i8* %globalptr
/external/llvm/test/Transforms/EarlyCSE/
Dbasic.ll200 %load1 = load i32, i32* %P1
201 %sel = select i1 %B, i32 %load0, i32 %load1
/external/llvm/test/CodeGen/SystemZ/
Dasm-18.ll716 %load1 = load i32 , i32 *%ptr1
717 %cmp1 = icmp sle i32 %res1, %load1
736 %load1 = load i32 , i32 *%ptr1
737 %cmp1 = icmp sle i32 %res1, %load1
/external/wpa_supplicant_8/wpa_supplicant/
Dinterworking.c2332 int bh1, bh2, load1, load2, conn1, conn2; in pick_best_roaming_partner() local
2334 load1 = cred_over_max_bss_load(wpa_s, cred, selected); in pick_best_roaming_partner()
2340 bh1, load1, conn1, bh2, load2, conn2); in pick_best_roaming_partner()
2341 if (bh1 || load1 || conn1 || !(bh2 || load2 || conn2)) { in pick_best_roaming_partner()
/external/valgrind/VEX/priv/
Dguest_tilegx_toIR.c132 IRExpr *load1 = NULL; in load() local
134 load1 = IRExpr_Load(Iend_LE, ty, addr); in load()
135 return load1; in load()

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