| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-shift.s | 299 rshrn2 v0.16b, v1.8h, #3
300 rshrn2 v0.8h, v1.4s, #3
301 rshrn2 v0.4s, v1.2d, #3
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| D | arm64-advsimd.s | 1307 rshrn2.16b v0, v0, #2
1309 rshrn2.8h v0, v0, #4
1311 rshrn2.4s v0, v0, #6
1479 ; CHECK: rshrn2.16b v0, v0, #2 ; encoding: [0x00,0x8c,0x0e,0x4f]
1481 ; CHECK: rshrn2.8h v0, v0, #4 ; encoding: [0x00,0x8c,0x1c,0x4f]
1483 ; CHECK: rshrn2.4s v0, v0, #6 ; encoding: [0x00,0x8c,0x3a,0x4f]
1648 rshrn2 v8.16b, v9.8h, #2
1650 rshrn2 v6.8h, v7.4s, #4
1652 rshrn2 v4.4s, v5.2d, #6
1719 ; CHECK: rshrn2.16b v8, v9, #2 ; encoding: [0x28,0x8d,0x0e,0x4f]
[all …]
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| D | neon-diagnostics.s | 1868 rshrn2 v0.16b, v1.8h, #17
1869 rshrn2 v0.8h, v1.4s, #33
1870 rshrn2 v0.4s, v1.2d, #65
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-simd-shift.ll | 368 ; CHECK: rshrn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.8h, #3
379 ; CHECK: rshrn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.4s, #9
390 ; CHECK: rshrn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.2d, #19
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| D | arm64-vecFold.ll | 98 ; CHECK-NEXT: rshrn2.16b v0, v2, #6
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| D | arm64-vshift.ll | 645 ;CHECK: rshrn2.16b v0, {{v[0-9]+}}, #1
655 ;CHECK: rshrn2.8h v0, {{v[0-9]+}}, #1
665 ;CHECK: rshrn2.4s v0, {{v[0-9]+}}, #1
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| /external/vixl/src/vixl/a64/ |
| D | logic-a64.cc | 2527 LogicVRegister Simulator::rshrn2(VectorFormat vform, in rshrn2() function in vixl::Simulator
2681 return rshrn2(vform, dst, src, shift).UnsignedSaturate(vform); in uqrshrn2()
3342 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in raddhn2()
3386 rshrn2(vform, dst, temp, LaneSizeInBitsFromFormat(vform)); in rsubhn2()
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| D | simulator-a64.h | 2201 LogicVRegister rshrn2(VectorFormat vform,
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| D | macro-assembler-a64.h | 2370 V(rshrn2, Rshrn2) \
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| D | assembler-a64.h | 3231 void rshrn2(const VRegister& vd,
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| D | simulator-a64.cc | 3825 rshrn2(vf, rd, rn, right_shift); in VisitNEONShiftImmediate()
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| D | assembler-a64.cc | 4376 void Assembler::rshrn2(const VRegister& vd, in rshrn2() function in vixl::Assembler
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 2033 # CHECK: rshrn2.16b v0, v0, #6
2035 # CHECK: rshrn2.8h v0, v0, #12
2037 # CHECK: rshrn2.4s v0, v0, #26
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| D | neon-instructions.txt | 989 # CHECK: rshrn2 v0.16b, v1.8h, #3
990 # CHECK: rshrn2 v0.8h, v1.4s, #3
991 # CHECK: rshrn2 v0.4s, v1.2d, #3
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 27491 rshrn2 v4.4s, v29.2d, #1 37504bd226ef2969239d20cb79b6e4f5 f7238a1daeeb282ed57ffecc46f208d7 d77…
27492 rshrn2 v4.4s, v29.2d, #32 1cc748e69a8e12192d1a490727a15463 9e032ba23f489352e512e49492f3f1a0 9e…
27495 rshrn2 v4.8h, v29.4s, #1 e93c190f33ee4cd836fc9169e3db77ed 1e1a025533fef6d8b0f5867e546ecd9a 012…
27496 rshrn2 v4.8h, v29.4s, #16 a394a6478ef9bcb2306bb10b7103fed1 c690e3c3cf33280015d4ef00cf02bbe5 c6…
27499 rshrn2 v4.16b, v29.8h, #1 f6a7496b02d2e287f95f0247b34ee01d 73ce92d7945ca60fafe62b266960e4b6 e76…
27500 rshrn2 v4.16b, v29.8h, #8 5ef2688a3398cbd170d20361e6423001 2817650c662db286f1a8d6ffe99ffce0 286…
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| /external/vixl/doc/ |
| D | supported-instructions.md | 2877 void rshrn2(const VRegister& vd,
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