Searched refs:uaddl2 (Results 1 – 16 of 16) sorted by relevance
| /external/llvm/test/MC/AArch64/ |
| D | neon-3vdiff.s | 41 uaddl2 v0.8h, v1.16b, v2.16b
42 uaddl2 v0.4s, v1.8h, v2.8h
43 uaddl2 v0.2d, v1.4s, v2.4s
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| D | arm64-advsimd.s | 1915 uaddl2 v9.8h, v13.16b, v14.16b
1917 uaddl2 v9.4s, v13.8h, v14.8h
1919 uaddl2 v9.2d, v13.4s, v14.4s
1921 ; CHECK: uaddl2.8h v9, v13, v14 ; encoding: [0xa9,0x01,0x2e,0x6e]
1923 ; CHECK: uaddl2.4s v9, v13, v14 ; encoding: [0xa9,0x01,0x6e,0x6e]
1925 ; CHECK: uaddl2.2d v9, v13, v14 ; encoding: [0xa9,0x01,0xae,0x6e]
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| D | neon-diagnostics.s | 2141 uaddl2 v0.8h, v1.16h, v2.16b
2142 uaddl2 v0.4s, v1.8s, v2.8h
2143 uaddl2 v0.2d, v1.4d, v2.4s
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vadd.ll | 243 ; CHECK-NEXT: uaddl2.8h v0, v0, v1
259 ; CHECK-NEXT: uaddl2.4s v0, v0, v1
275 ; CHECK-NEXT: uaddl2.2d v0, v0, v1
744 ; CHECK: uaddl2.2d
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| D | arm64-neon-3vdiff.ll | 151 ; CHECK: uaddl2 {{v[0-9]+}}.8h, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
163 ; CHECK: uaddl2 {{v[0-9]+}}.4s, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
175 ; CHECK: uaddl2 {{v[0-9]+}}.2d, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
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| /external/libavc/common/armv8/ |
| D | ih264_intra_pred_luma_16x16_av8.s | 324 uaddl2 v3.8h, v0.16b, v1.16b
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| /external/libavc/encoder/armv8/ |
| D | ih264e_evaluate_intra16x16_modes_av8.s | 130 uaddl2 v3.8h, v0.16b, v1.16b
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | neon-instructions.txt | 1146 # CHECK: uaddl2 v0.8h, v1.16b, v2.16b
1147 # CHECK: uaddl2 v0.4s, v1.8h, v2.8h
1148 # CHECK: uaddl2 v0.2d, v1.4s, v2.4s
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.h | 1947 LogicVRegister uaddl2(VectorFormat vform,
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| D | macro-assembler-a64.h | 2179 V(uaddl2, Uaddl2) \
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| D | assembler-a64.h | 3043 void uaddl2(const VRegister& vd,
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| D | simulator-a64.cc | 2758 case NEON_UADDL2: uaddl2(vf_l, rd, rn, rm); break; in VisitNEON3Different()
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| D | logic-a64.cc | 2793 LogicVRegister Simulator::uaddl2(VectorFormat vform, in uaddl2() function in vixl::Simulator
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| D | assembler-a64.cc | 2388 V(uaddl2, NEON_UADDL2, vn.IsVector() && vn.IsQ()) \
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| /external/vixl/doc/ |
| D | supported-instructions.md | 4065 void uaddl2(const VRegister& vd,
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| /external/valgrind/none/tests/arm64/ |
| D | fp_and_simd.stdout.exp | 27382 uaddl2 v2.2d, v11.4s, v29.4s 52b73571557c52622fab85bf23c6ccce e484440f14df0338ef5a9979278f2c5a …
27384 uaddl2 v2.4s, v11.8h, v29.8h d634de94bf2a68d55c2818405e15298f 3b4e64f4a9e03b9827d7407754b35a12 …
27386 uaddl2 v2.8h, v11.16b, v29.16b 39dd6a423e27a49218fcc32356c26e69 e92bf4c9aa96ae065cde651d98a487e7…
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