1 //==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Hexagon implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
16 #define LLVM_LIB_TARGET_HEXAGON_HEXAGONREGISTERINFO_H
17 
18 #include "llvm/MC/MachineLocation.h"
19 #include "llvm/Target/TargetRegisterInfo.h"
20 
21 #define GET_REGINFO_HEADER
22 #include "HexagonGenRegisterInfo.inc"
23 
24 //
25 //  We try not to hard code the reserved registers in our code,
26 //  so the following two macros were defined. However, there
27 //  are still a few places that R11 and R10 are hard wired.
28 //  See below. If, in the future, we decided to change the reserved
29 //  register. Don't forget changing the following places.
30 //
31 //  1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
32 //  2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
33 //  3. the definition of "IntRegs" in HexagonRegisterInfo.td
34 //  4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
35 //
36 #define HEXAGON_RESERVED_REG_1 Hexagon::R10
37 #define HEXAGON_RESERVED_REG_2 Hexagon::R11
38 
39 namespace llvm {
40 struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
41   HexagonRegisterInfo();
42 
43   /// Code Generation virtual methods...
44   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
45 
46   const TargetRegisterClass* const*
47   getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const;
48 
49   BitVector getReservedRegs(const MachineFunction &MF) const override;
50 
51   void eliminateFrameIndex(MachineBasicBlock::iterator II,
52                            int SPAdj, unsigned FIOperandNum,
53                            RegScavenger *RS = nullptr) const override;
54 
55   /// determineFrameLayout - Determine the size of the frame and maximum call
56   /// frame size.
57   void determineFrameLayout(MachineFunction &MF) const;
58 
59   /// requiresRegisterScavenging - returns true since we may need scavenging for
60   /// a temporary register when generating hardware loop instructions.
requiresRegisterScavengingHexagonRegisterInfo61   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
62     return true;
63   }
64 
trackLivenessAfterRegAllocHexagonRegisterInfo65   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
66     return true;
67   }
68 
69   // Debug information queries.
70   unsigned getRARegister() const;
71   unsigned getFrameRegister(const MachineFunction &MF) const override;
72   unsigned getFrameRegister() const;
73   unsigned getStackRegister() const;
74 };
75 
76 } // end namespace llvm
77 
78 #endif
79