• Home
  • History
  • Annotate
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1  // Copyright 2015, ARM Limited
2  // All rights reserved.
3  //
4  // Redistribution and use in source and binary forms, with or without
5  // modification, are permitted provided that the following conditions are met:
6  //
7  //   * Redistributions of source code must retain the above copyright notice,
8  //     this list of conditions and the following disclaimer.
9  //   * Redistributions in binary form must reproduce the above copyright notice,
10  //     this list of conditions and the following disclaimer in the documentation
11  //     and/or other materials provided with the distribution.
12  //   * Neither the name of ARM Limited nor the names of its contributors may be
13  //     used to endorse or promote products derived from this software without
14  //     specific prior written permission.
15  //
16  // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17  // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18  // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19  // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20  // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22  // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23  // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24  // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25  // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  
27  
28  // ---------------------------------------------------------------------
29  // This file is auto generated using tools/generate_simulator_traces.py.
30  //
31  // PLEASE DO NOT EDIT.
32  // ---------------------------------------------------------------------
33  
34  #ifndef VIXL_SIM_SADDLP_8H_TRACE_A64_H_
35  #define VIXL_SIM_SADDLP_8H_TRACE_A64_H_
36  
37  const uint16_t kExpected_NEON_saddlp_8H[] = {
38    0x0088, 0x00fb, 0xffff, 0xff03, 0xff2d, 0xffc4, 0xfffb, 0xffff,
39    0x00d2, 0x00fd, 0xff01, 0xff05, 0xff76, 0xfff5, 0xfffd, 0x0001,
40    0x00fb, 0xffff, 0xff03, 0xff2d, 0xffc4, 0xfffb, 0xffff, 0x0003,
41    0x00fd, 0xff01, 0xff05, 0xff76, 0xfff5, 0xfffd, 0x0001, 0x000a,
42    0xffff, 0xff03, 0xff2d, 0xffc4, 0xfffb, 0xffff, 0x0003, 0x003b,
43    0xff01, 0xff05, 0xff76, 0xfff5, 0xfffd, 0x0001, 0x000a, 0x0088,
44    0xff03, 0xff2d, 0xffc4, 0xfffb, 0xffff, 0x0003, 0x003b, 0x00d2,
45    0xff05, 0xff76, 0xfff5, 0xfffd, 0x0001, 0x000a, 0x0088, 0x00fb,
46    0xff2d, 0xffc4, 0xfffb, 0xffff, 0x0003, 0x003b, 0x00d2, 0x00fd,
47    0xff76, 0xfff5, 0xfffd, 0x0001, 0x000a, 0x0088, 0x00fb, 0xffff,
48    0xffc4, 0xfffb, 0xffff, 0x0003, 0x003b, 0x00d2, 0x00fd, 0xff01,
49    0xfff5, 0xfffd, 0x0001, 0x000a, 0x0088, 0x00fb, 0xffff, 0xff03,
50    0xfffb, 0xffff, 0x0003, 0x003b, 0x00d2, 0x00fd, 0xff01, 0xff05,
51    0xfffd, 0x0001, 0x000a, 0x0088, 0x00fb, 0xffff, 0xff03, 0xff2d,
52    0xffff, 0x0003, 0x003b, 0x00d2, 0x00fd, 0xff01, 0xff05, 0xff76,
53    0x0001, 0x000a, 0x0088, 0x00fb, 0xffff, 0xff03, 0xff2d, 0xffc4,
54    0x0003, 0x003b, 0x00d2, 0x00fd, 0xff01, 0xff05, 0xff76, 0xfff5,
55    0x000a, 0x0088, 0x00fb, 0xffff, 0xff03, 0xff2d, 0xffc4, 0xfffb,
56    0x003b, 0x00d2, 0x00fd, 0xff01, 0xff05, 0xff76, 0xfff5, 0xfffd,
57  };
58  const unsigned kExpectedCount_NEON_saddlp_8H = 19;
59  
60  #endif  // VIXL_SIM_SADDLP_8H_TRACE_A64_H_
61