1881   Mips64ManagedRegister dst = m_dst.AsMips64();  in EmitLoad()
1995     GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister();  in BuildFrame()
2001   StoreToOffset(kStoreDoubleword, method_reg.AsMips64().AsGpuRegister(), SP, 0);  in BuildFrame()
2006     Mips64ManagedRegister reg = entry_spills.at(i).AsMips64();  in BuildFrame()
2033     GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister();  in RemoveFrame()
2068   Mips64ManagedRegister src = msrc.AsMips64();  in Store()
2093   Mips64ManagedRegister src = msrc.AsMips64();  in StoreRef()
2099   Mips64ManagedRegister src = msrc.AsMips64();  in StoreRawPtr()
2106   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreImmediateToFrame()
2115   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreStackOffsetToThread64()
2127   Mips64ManagedRegister src = msrc.AsMips64();  in StoreSpanning()
2128   Mips64ManagedRegister scratch = mscratch.AsMips64();  in StoreSpanning()
2145   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRef()
2152   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRef()
2153   CHECK(dest.IsGpuRegister() && base.AsMips64().IsGpuRegister());  in LoadRef()
2155                  base.AsMips64().AsGpuRegister(), offs.Int32Value());  in LoadRef()
2167   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRawPtr()
2168   CHECK(dest.IsGpuRegister() && base.AsMips64().IsGpuRegister());  in LoadRawPtr()
2170                  base.AsMips64().AsGpuRegister(), offs.Int32Value());  in LoadRawPtr()
2175   Mips64ManagedRegister dest = mdest.AsMips64();  in LoadRawPtrFromThread64()
2191   Mips64ManagedRegister dest = mdest.AsMips64();  in Move()
2192   Mips64ManagedRegister src = msrc.AsMips64();  in Move()
2212   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRef()
2221   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRawPtrFromThread64()
2230   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CopyRawPtrToThread64()
2240   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Copy()
2256   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()
2259     LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(),  in Copy()
2263     LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(),  in Copy()
2273   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()
2277     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),  in Copy()
2281     StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(),  in Copy()
2299   GpuRegister scratch = mscratch.AsMips64().AsGpuRegister();  in Copy()
2302     LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value());  in Copy()
2303 …StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value()…  in Copy()
2305     LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(),  in Copy()
2307     StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(),  in Copy()
2332   Mips64ManagedRegister out_reg = mout_reg.AsMips64();  in CreateHandleScopeEntry()
2333   Mips64ManagedRegister in_reg = min_reg.AsMips64();  in CreateHandleScopeEntry()
2361   Mips64ManagedRegister scratch = mscratch.AsMips64();  in CreateHandleScopeEntry()
2382   Mips64ManagedRegister out_reg = mout_reg.AsMips64();  in LoadReferenceFromHandleScope()
2383   Mips64ManagedRegister in_reg = min_reg.AsMips64();  in LoadReferenceFromHandleScope()
2407   Mips64ManagedRegister base = mbase.AsMips64();  in Call()
2408   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Call()
2419   Mips64ManagedRegister scratch = mscratch.AsMips64();  in Call()
2437   Move(tr.AsMips64().AsGpuRegister(), S1);  in GetCurrentThread()
2446   Mips64ManagedRegister scratch = mscratch.AsMips64();  in ExceptionPoll()