1835 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) {  in shll()  argument
1836   EmitGenericShift(false, 4, operand, shifter);  in shll()
1840 void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) {  in shlq()  argument
1841   EmitGenericShift(true, 4, operand, shifter);  in shlq()
1855 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) {  in shrl()  argument
1856   EmitGenericShift(false, 5, operand, shifter);  in shrl()
1860 void X86_64Assembler::shrq(CpuRegister operand, CpuRegister shifter) {  in shrq()  argument
1861   EmitGenericShift(true, 5, operand, shifter);  in shrq()
1870 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) {  in sarl()  argument
1871   EmitGenericShift(false, 7, operand, shifter);  in sarl()
1880 void X86_64Assembler::sarq(CpuRegister operand, CpuRegister shifter) {  in sarq()  argument
1881   EmitGenericShift(true, 7, operand, shifter);  in sarq()
1890 void X86_64Assembler::roll(CpuRegister operand, CpuRegister shifter) {  in roll()  argument
1891   EmitGenericShift(false, 0, operand, shifter);  in roll()
1900 void X86_64Assembler::rorl(CpuRegister operand, CpuRegister shifter) {  in rorl()  argument
1901   EmitGenericShift(false, 1, operand, shifter);  in rorl()
1910 void X86_64Assembler::rolq(CpuRegister operand, CpuRegister shifter) {  in rolq()  argument
1911   EmitGenericShift(true, 0, operand, shifter);  in rolq()
1920 void X86_64Assembler::rorq(CpuRegister operand, CpuRegister shifter) {  in rorq()  argument
1921   EmitGenericShift(true, 1, operand, shifter);  in rorq()
2377 void X86_64Assembler::EmitOperand(uint8_t reg_or_opcode, const Operand& operand) {  in EmitOperand()  argument
2380   const int length = operand.length_;  in EmitOperand()
2383   CHECK_EQ(operand.encoding_[0] & 0x38, 0);  in EmitOperand()
2384   EmitUint8(operand.encoding_[0] + (reg_or_opcode << 3));  in EmitOperand()
2387     EmitUint8(operand.encoding_[i]);  in EmitOperand()
2389   AssemblerFixup* fixup = operand.GetFixup();  in EmitOperand()
2406                                   const Operand& operand,  in EmitComplex()  argument
2413     EmitOperand(reg_or_opcode, operand);  in EmitComplex()
2415   } else if (operand.IsRegister(CpuRegister(RAX))) {  in EmitComplex()
2421     EmitOperand(reg_or_opcode, operand);  in EmitComplex()
2485                                        CpuRegister operand,  in EmitGenericShift()  argument
2490     EmitRex64(operand);  in EmitGenericShift()
2492     EmitOptionalRex32(operand);  in EmitGenericShift()
2495   EmitOperand(reg_or_opcode, Operand(operand));  in EmitGenericShift()
2542 void X86_64Assembler::EmitOptionalRex32(const Operand& operand) {  in EmitOptionalRex32()  argument
2543   uint8_t rex = operand.rex();  in EmitOptionalRex32()
2549 void X86_64Assembler::EmitOptionalRex32(CpuRegister dst, const Operand& operand) {  in EmitOptionalRex32()  argument
2550   uint8_t rex = operand.rex();  in EmitOptionalRex32()
2559 void X86_64Assembler::EmitOptionalRex32(XmmRegister dst, const Operand& operand) {  in EmitOptionalRex32()  argument
2560   uint8_t rex = operand.rex();  in EmitOptionalRex32()
2577 void X86_64Assembler::EmitRex64(const Operand& operand) {  in EmitRex64()  argument
2578   uint8_t rex = operand.rex();  in EmitRex64()
2595 void X86_64Assembler::EmitRex64(CpuRegister dst, const Operand& operand) {  in EmitRex64()  argument
2596   uint8_t rex = 0x48 | operand.rex();  // REX.W000  in EmitRex64()
2603 void X86_64Assembler::EmitRex64(XmmRegister dst, const Operand& operand) {  in EmitRex64()  argument
2604   uint8_t rex = 0x48 | operand.rex();  // REX.W000  in EmitRex64()
2617 void X86_64Assembler::EmitOptionalByteRegNormalizingRex32(CpuRegister dst, const Operand& operand) {  in EmitOptionalByteRegNormalizingRex32()  argument
2618   uint8_t rex = operand.rex();  in EmitOptionalByteRegNormalizingRex32()