Lines Matching refs:hw_info
112 struct radeon_hw_info hw_info; member
207 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
210 surf_man->hw_info.allow_2d = 1; in r6_init_hw_info()
216 surf_man->hw_info.num_pipes = 1; in r6_init_hw_info()
219 surf_man->hw_info.num_pipes = 2; in r6_init_hw_info()
222 surf_man->hw_info.num_pipes = 4; in r6_init_hw_info()
225 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
228 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
229 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
235 surf_man->hw_info.num_banks = 4; in r6_init_hw_info()
238 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
241 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
242 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
248 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
251 surf_man->hw_info.group_bytes = 512; in r6_init_hw_info()
254 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
255 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
270 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear()
275 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
304 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear_aligned()
306 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
332 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
340 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_1d()
366 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / in r6_surface_init_2d()
368 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); in r6_surface_init_2d()
371 yalign = tilew * surf_man->hw_info.num_pipes; in r6_surface_init_2d()
377 MAX2(surf_man->hw_info.num_pipes * in r6_surface_init_2d()
378 surf_man->hw_info.num_banks * in r6_surface_init_2d()
429 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in r6_surface_init()
492 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
495 surf_man->hw_info.allow_2d = 1; in eg_init_hw_info()
501 surf_man->hw_info.num_pipes = 1; in eg_init_hw_info()
504 surf_man->hw_info.num_pipes = 2; in eg_init_hw_info()
507 surf_man->hw_info.num_pipes = 4; in eg_init_hw_info()
510 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
513 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
514 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
520 surf_man->hw_info.num_banks = 4; in eg_init_hw_info()
523 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
526 surf_man->hw_info.num_banks = 16; in eg_init_hw_info()
529 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
530 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
536 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
539 surf_man->hw_info.group_bytes = 512; in eg_init_hw_info()
542 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
543 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
549 surf_man->hw_info.row_size = 1024; in eg_init_hw_info()
552 surf_man->hw_info.row_size = 2048; in eg_init_hw_info()
555 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
558 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
559 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
617 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); in eg_surface_init_1d()
626 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in eg_surface_init_1d()
670 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
671 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
717 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in eg_surface_sanity()
751 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
775 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
916 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
919 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
967 surf->tile_split = surf_man->hw_info.row_size; in eg_surface_best()
968 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
1006 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1011 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / in eg_surface_best()
1012 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1204 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1207 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in si_init_hw_info()
1208 surf_man->hw_info.allow_2d = 1; in si_init_hw_info()
1215 surf_man->hw_info.num_pipes = 1; in si_init_hw_info()
1218 surf_man->hw_info.num_pipes = 2; in si_init_hw_info()
1221 surf_man->hw_info.num_pipes = 4; in si_init_hw_info()
1224 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1227 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1228 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1234 surf_man->hw_info.num_banks = 4; in si_init_hw_info()
1237 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1240 surf_man->hw_info.num_banks = 16; in si_init_hw_info()
1243 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1244 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1250 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1253 surf_man->hw_info.group_bytes = 512; in si_init_hw_info()
1256 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1257 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1263 surf_man->hw_info.row_size = 1024; in si_init_hw_info()
1266 surf_man->hw_info.row_size = 2048; in si_init_hw_info()
1269 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1272 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1273 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1297 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in si_surface_sanity()
1340 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode]; in si_surface_sanity()
1391 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode]; in si_surface_sanity()
1520 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1525 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1550 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_1d()
1557 slice_align = surf_man->hw_info.group_bytes; in si_surface_init_1d()
1703 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in si_surface_init_2d_miptrees()
1860 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in cik_get_2d_params()
1938 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_get_2d_params()
1946 gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index]; in cik_get_2d_params()
2033 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2036 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in cik_init_hw_info()
2037 …!radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_… in cik_init_hw_info()
2038 surf_man->hw_info.allow_2d = 1; in cik_init_hw_info()
2045 surf_man->hw_info.num_pipes = 1; in cik_init_hw_info()
2048 surf_man->hw_info.num_pipes = 2; in cik_init_hw_info()
2051 surf_man->hw_info.num_pipes = 4; in cik_init_hw_info()
2054 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2057 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2058 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2064 surf_man->hw_info.num_banks = 4; in cik_init_hw_info()
2067 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2070 surf_man->hw_info.num_banks = 16; in cik_init_hw_info()
2073 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2074 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2080 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2083 surf_man->hw_info.group_bytes = 512; in cik_init_hw_info()
2086 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2087 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2093 surf_man->hw_info.row_size = 1024; in cik_init_hw_info()
2096 surf_man->hw_info.row_size = 2048; in cik_init_hw_info()
2099 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2102 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2103 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2125 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in cik_surface_sanity()
2227 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_surface_init_2d()