Lines Matching refs:surf
91 struct radeon_surface *surf);
93 struct radeon_surface *surf);
162 static void surf_minify(struct radeon_surface *surf, in surf_minify() argument
168 surflevel->npix_x = mip_minify(surf->npix_x, level); in surf_minify()
169 surflevel->npix_y = mip_minify(surf->npix_y, level); in surf_minify()
170 surflevel->npix_z = mip_minify(surf->npix_z, level); in surf_minify()
171 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in surf_minify()
172 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in surf_minify()
173 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in surf_minify()
174 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D && in surf_minify()
175 !(surf->flags & RADEON_SURF_FMASK)) { in surf_minify()
186 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in surf_minify()
189 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in surf_minify()
262 struct radeon_surface *surf, in r6_surface_init_linear() argument
270 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear()
275 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
278 if (surf->flags & RADEON_SURF_SCANOUT) { in r6_surface_init_linear()
279 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_linear()
283 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_linear()
284 surf->level[i].mode = RADEON_SURF_MODE_LINEAR; in r6_surface_init_linear()
285 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear()
287 offset = surf->bo_size; in r6_surface_init_linear()
289 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_linear()
296 struct radeon_surface *surf, in r6_surface_init_linear_aligned() argument
304 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear_aligned()
306 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
311 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_linear_aligned()
312 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in r6_surface_init_linear_aligned()
313 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_linear_aligned()
315 offset = surf->bo_size; in r6_surface_init_linear_aligned()
317 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_linear_aligned()
324 struct radeon_surface *surf, in r6_surface_init_1d() argument
332 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
336 if (surf->flags & RADEON_SURF_SCANOUT) { in r6_surface_init_1d()
337 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_1d()
340 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_1d()
344 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_1d()
345 surf->level[i].mode = RADEON_SURF_MODE_1D; in r6_surface_init_1d()
346 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_1d()
348 offset = surf->bo_size; in r6_surface_init_1d()
350 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_1d()
357 struct radeon_surface *surf, in r6_surface_init_2d() argument
367 (tilew * surf->bpe * surf->nsamples); in r6_surface_init_2d()
369 if (surf->flags & RADEON_SURF_FMASK) in r6_surface_init_2d()
372 if (surf->flags & RADEON_SURF_SCANOUT) { in r6_surface_init_2d()
373 xalign = MAX2((surf->bpe == 1) ? 64 : 32, xalign); in r6_surface_init_2d()
376 surf->bo_alignment = in r6_surface_init_2d()
379 surf->nsamples * surf->bpe * 64, in r6_surface_init_2d()
380 xalign * yalign * surf->nsamples * surf->bpe); in r6_surface_init_2d()
384 for (i = start_level; i <= surf->last_level; i++) { in r6_surface_init_2d()
385 surf->level[i].mode = RADEON_SURF_MODE_2D; in r6_surface_init_2d()
386 surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, offset); in r6_surface_init_2d()
387 if (surf->level[i].mode == RADEON_SURF_MODE_1D) { in r6_surface_init_2d()
388 return r6_surface_init_1d(surf_man, surf, offset, i); in r6_surface_init_2d()
391 offset = surf->bo_size; in r6_surface_init_2d()
393 offset = ALIGN(offset, surf->bo_alignment); in r6_surface_init_2d()
400 struct radeon_surface *surf) in r6_surface_init() argument
406 if (surf->nsamples > 1) { in r6_surface_init()
407 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in r6_surface_init()
408 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in r6_surface_init()
412 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in r6_surface_init()
414 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in r6_surface_init()
422 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in r6_surface_init()
423 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in r6_surface_init()
430 if (surf->nsamples > 1) { in r6_surface_init()
435 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in r6_surface_init()
436 surf->flags |= RADEON_SURF_SET(mode, MODE); in r6_surface_init()
440 if (surf->npix_x > 8192 || surf->npix_y > 8192 || surf->npix_z > 8192) { in r6_surface_init()
445 if (surf->last_level > 14) { in r6_surface_init()
452 r = r6_surface_init_linear(surf_man, surf, 0, 0); in r6_surface_init()
455 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in r6_surface_init()
458 r = r6_surface_init_1d(surf_man, surf, 0, 0); in r6_surface_init()
461 r = r6_surface_init_2d(surf_man, surf, 0, 0); in r6_surface_init()
470 struct radeon_surface *surf) in r6_surface_best() argument
565 static void eg_surf_minify(struct radeon_surface *surf, in eg_surf_minify() argument
577 surflevel->npix_x = mip_minify(surf->npix_x, level); in eg_surf_minify()
578 surflevel->npix_y = mip_minify(surf->npix_y, level); in eg_surf_minify()
579 surflevel->npix_z = mip_minify(surf->npix_z, level); in eg_surf_minify()
580 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in eg_surf_minify()
581 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in eg_surf_minify()
582 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in eg_surf_minify()
583 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D && in eg_surf_minify()
584 !(surf->flags & RADEON_SURF_FMASK)) { in eg_surf_minify()
600 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in eg_surf_minify()
603 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in eg_surf_minify()
607 struct radeon_surface *surf, in eg_surface_init_1d() argument
617 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); in eg_surface_init_1d()
621 if (surf->flags & RADEON_SURF_SCANOUT) { in eg_surface_init_1d()
627 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in eg_surface_init_1d()
635 for (i = start_level; i <= surf->last_level; i++) { in eg_surface_init_1d()
637 surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, offset); in eg_surface_init_1d()
639 offset = surf->bo_size; in eg_surface_init_1d()
641 offset = ALIGN(offset, surf->bo_alignment); in eg_surface_init_1d()
648 struct radeon_surface *surf, in eg_surface_init_2d() argument
661 tileb = tilew * tileh * bpe * surf->nsamples; in eg_surface_init_2d()
670 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
671 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
677 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in eg_surface_init_2d()
685 for (i = start_level; i <= surf->last_level; i++) { in eg_surface_init_2d()
687 eg_surf_minify(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, mtileb, offset); in eg_surface_init_2d()
689 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i); in eg_surface_init_2d()
692 offset = surf->bo_size; in eg_surface_init_2d()
694 offset = ALIGN(offset, surf->bo_alignment); in eg_surface_init_2d()
701 struct radeon_surface *surf, in eg_surface_sanity() argument
707 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { in eg_surface_sanity()
712 if (surf->last_level > 15) { in eg_surface_sanity()
718 if (surf->nsamples > 1) { in eg_surface_sanity()
723 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in eg_surface_sanity()
724 surf->flags |= RADEON_SURF_SET(mode, MODE); in eg_surface_sanity()
729 switch (surf->tile_split) { in eg_surface_sanity()
741 switch (surf->mtilea) { in eg_surface_sanity()
751 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
755 switch (surf->bankw) { in eg_surface_sanity()
765 switch (surf->bankh) { in eg_surface_sanity()
774 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); in eg_surface_sanity()
775 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
784 struct radeon_surface *surf) in eg_surface_init_1d_miptrees() argument
787 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags; in eg_surface_init_1d_miptrees()
791 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_1d_miptrees()
793 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0); in eg_surface_init_1d_miptrees()
798 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, in eg_surface_init_1d_miptrees()
799 surf->bo_size, 0); in eg_surface_init_1d_miptrees()
800 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_1d_miptrees()
806 struct radeon_surface *surf) in eg_surface_init_2d_miptrees() argument
809 int r, is_depth_stencil = (surf->flags & zs_flags) == zs_flags; in eg_surface_init_2d_miptrees()
813 (surf->flags & RADEON_SURF_HAS_SBUFFER_MIPTREE) ? surf->stencil_level : tmp; in eg_surface_init_2d_miptrees()
815 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe, in eg_surface_init_2d_miptrees()
816 surf->tile_split, 0, 0); in eg_surface_init_2d_miptrees()
821 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, in eg_surface_init_2d_miptrees()
822 surf->stencil_tile_split, surf->bo_size, 0); in eg_surface_init_2d_miptrees()
823 surf->stencil_offset = stencil_level[0].offset; in eg_surface_init_2d_miptrees()
829 struct radeon_surface *surf) in eg_surface_init() argument
835 if (surf->nsamples > 1) { in eg_surface_init()
836 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in eg_surface_init()
837 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in eg_surface_init()
841 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in eg_surface_init()
843 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in eg_surface_init()
851 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in eg_surface_init()
852 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in eg_surface_init()
857 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_init()
862 surf->stencil_offset = 0; in eg_surface_init()
863 surf->bo_alignment = 0; in eg_surface_init()
868 r = r6_surface_init_linear(surf_man, surf, 0, 0); in eg_surface_init()
871 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in eg_surface_init()
874 r = eg_surface_init_1d_miptrees(surf_man, surf); in eg_surface_init()
877 r = eg_surface_init_2d_miptrees(surf_man, surf); in eg_surface_init()
904 struct radeon_surface *surf) in eg_surface_best() argument
910 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in eg_surface_best()
913 surf->tile_split = 1024; in eg_surface_best()
914 surf->bankw = 1; in eg_surface_best()
915 surf->bankh = 1; in eg_surface_best()
916 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
917 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); in eg_surface_best()
918 for (; surf->bankh <= 8; surf->bankh *= 2) { in eg_surface_best()
919 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
923 if (surf->mtilea > 8) { in eg_surface_best()
924 surf->mtilea = 8; in eg_surface_best()
927 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_best()
938 if (surf->nsamples > 1) { in eg_surface_best()
939 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in eg_surface_best()
940 switch (surf->nsamples) { in eg_surface_best()
942 surf->tile_split = 128; in eg_surface_best()
945 surf->tile_split = 128; in eg_surface_best()
948 surf->tile_split = 256; in eg_surface_best()
951 surf->tile_split = 512; in eg_surface_best()
955 surf->nsamples, __LINE__); in eg_surface_best()
958 surf->stencil_tile_split = 64; in eg_surface_best()
961 surf->tile_split = MAX2(surf->nsamples * surf->bpe * 64, 256); in eg_surface_best()
962 if (surf->tile_split > 4096) in eg_surface_best()
963 surf->tile_split = 4096; in eg_surface_best()
967 surf->tile_split = surf_man->hw_info.row_size; in eg_surface_best()
968 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
979 if (surf->flags & RADEON_SURF_SBUFFER) { in eg_surface_best()
983 tileb = MIN2(surf->tile_split, 64 * surf->nsamples); in eg_surface_best()
985 tileb = MIN2(surf->tile_split, 64 * surf->bpe * surf->nsamples); in eg_surface_best()
991 surf->bankw = 1; in eg_surface_best()
994 surf->bankh = 4; in eg_surface_best()
998 surf->bankh = 2; in eg_surface_best()
1001 surf->bankh = 1; in eg_surface_best()
1005 for (; surf->bankh <= 8; surf->bankh *= 2) { in eg_surface_best()
1006 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1011 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / in eg_surface_best()
1012 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1013 surf->mtilea = 1 << (log2_int(h_over_w) >> 1); in eg_surface_best()
1280 struct radeon_surface *surf, in si_surface_sanity() argument
1286 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { in si_surface_sanity()
1291 if (surf->last_level > 15) { in si_surface_sanity()
1297 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in si_surface_sanity()
1298 if (surf->nsamples > 1) { in si_surface_sanity()
1303 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_sanity()
1304 surf->flags |= RADEON_SURF_SET(mode, MODE); in si_surface_sanity()
1307 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) { in si_surface_sanity()
1311 if (!surf->tile_split) { in si_surface_sanity()
1313 surf->mtilea = 1; in si_surface_sanity()
1314 surf->bankw = 1; in si_surface_sanity()
1315 surf->bankh = 1; in si_surface_sanity()
1316 surf->tile_split = 64; in si_surface_sanity()
1317 surf->stencil_tile_split = 64; in si_surface_sanity()
1322 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_sanity()
1323 switch (surf->nsamples) { in si_surface_sanity()
1341 si_gb_tile_mode(gb_tile_mode, NULL, NULL, NULL, NULL, NULL, &surf->stencil_tile_split); in si_surface_sanity()
1343 if (surf->flags & RADEON_SURF_ZBUFFER) { in si_surface_sanity()
1344 switch (surf->nsamples) { in si_surface_sanity()
1360 } else if (surf->flags & RADEON_SURF_SCANOUT) { in si_surface_sanity()
1361 switch (surf->bpe) { in si_surface_sanity()
1372 switch (surf->bpe) { in si_surface_sanity()
1392 …si_gb_tile_mode(gb_tile_mode, NULL, NULL, &surf->mtilea, &surf->bankw, &surf->bankh, &surf->tile_s… in si_surface_sanity()
1395 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_sanity()
1398 if (surf->flags & RADEON_SURF_ZBUFFER) { in si_surface_sanity()
1400 } else if (surf->flags & RADEON_SURF_SCANOUT) { in si_surface_sanity()
1414 static void si_surf_minify(struct radeon_surface *surf, in si_surf_minify() argument
1421 surflevel->npix_x = surf->npix_x; in si_surf_minify()
1423 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level); in si_surf_minify()
1425 surflevel->npix_y = mip_minify(surf->npix_y, level); in si_surf_minify()
1426 surflevel->npix_z = mip_minify(surf->npix_z, level); in si_surf_minify()
1428 if (level == 0 && surf->last_level > 0) { in si_surf_minify()
1429 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w; in si_surf_minify()
1430 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
1431 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d; in si_surf_minify()
1433 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in si_surf_minify()
1434 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in si_surf_minify()
1435 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in si_surf_minify()
1443 if (level == 0 && surf->last_level == 0) in si_surf_minify()
1446 xalign = MAX2(xalign, slice_align / surf->bpe); in si_surf_minify()
1455 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in si_surf_minify()
1459 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in si_surf_minify()
1462 static void si_surf_minify_2d(struct radeon_surface *surf, in si_surf_minify_2d() argument
1471 surflevel->npix_x = surf->npix_x; in si_surf_minify_2d()
1473 surflevel->npix_x = mip_minify(next_power_of_two(surf->npix_x), level); in si_surf_minify_2d()
1475 surflevel->npix_y = mip_minify(surf->npix_y, level); in si_surf_minify_2d()
1476 surflevel->npix_z = mip_minify(surf->npix_z, level); in si_surf_minify_2d()
1478 if (level == 0 && surf->last_level > 0) { in si_surf_minify_2d()
1479 surflevel->nblk_x = (next_power_of_two(surflevel->npix_x) + surf->blk_w - 1) / surf->blk_w; in si_surf_minify_2d()
1480 surflevel->nblk_y = (next_power_of_two(surflevel->npix_y) + surf->blk_h - 1) / surf->blk_h; in si_surf_minify_2d()
1481 surflevel->nblk_z = (next_power_of_two(surflevel->npix_z) + surf->blk_d - 1) / surf->blk_d; in si_surf_minify_2d()
1483 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; in si_surf_minify_2d()
1484 surflevel->nblk_y = (surflevel->npix_y + surf->blk_h - 1) / surf->blk_h; in si_surf_minify_2d()
1485 surflevel->nblk_z = (surflevel->npix_z + surf->blk_d - 1) / surf->blk_d; in si_surf_minify_2d()
1488 if (surf->nsamples == 1 && surflevel->mode == RADEON_SURF_MODE_2D && in si_surf_minify_2d()
1489 !(surf->flags & RADEON_SURF_FMASK)) { in si_surf_minify_2d()
1504 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; in si_surf_minify_2d()
1507 surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size; in si_surf_minify_2d()
1511 struct radeon_surface *surf, in si_surface_init_linear_aligned() argument
1520 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1522 xalign = MAX2(8, 64 / surf->bpe); in si_surface_init_linear_aligned()
1525 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1528 for (i = start_level; i <= surf->last_level; i++) { in si_surface_init_linear_aligned()
1529 surf->level[i].mode = RADEON_SURF_MODE_LINEAR_ALIGNED; in si_surface_init_linear_aligned()
1530 … si_surf_minify(surf, surf->level+i, surf->bpe, i, xalign, yalign, zalign, slice_align, offset); in si_surface_init_linear_aligned()
1532 offset = surf->bo_size; in si_surface_init_linear_aligned()
1534 offset = ALIGN(offset, surf->bo_alignment); in si_surface_init_linear_aligned()
1536 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in si_surface_init_linear_aligned()
1537 surf->tiling_index[i] = tile_mode; in si_surface_init_linear_aligned()
1544 struct radeon_surface *surf, in si_surface_init_1d() argument
1558 if (surf->flags & RADEON_SURF_SCANOUT) { in si_surface_init_1d()
1563 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in si_surface_init_1d()
1571 for (i = start_level; i <= surf->last_level; i++) { in si_surface_init_1d()
1573 si_surf_minify(surf, level+i, bpe, i, xalign, yalign, zalign, slice_align, offset); in si_surface_init_1d()
1575 offset = surf->bo_size; in si_surface_init_1d()
1579 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in si_surface_init_1d()
1580 if (surf->level == level) { in si_surface_init_1d()
1581 surf->tiling_index[i] = tile_mode; in si_surface_init_1d()
1583 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_1d()
1585 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_1d()
1593 struct radeon_surface *surf, in si_surface_init_1d_miptrees() argument
1598 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0); in si_surface_init_1d_miptrees()
1603 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_init_1d_miptrees()
1604 …r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0… in si_surface_init_1d_miptrees()
1605 surf->stencil_offset = surf->stencil_level[0].offset; in si_surface_init_1d_miptrees()
1611 struct radeon_surface *surf, in si_surface_init_2d() argument
1628 tileb = tilew * tileh * bpe * surf->nsamples; in si_surface_init_2d()
1637 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea; in si_surface_init_2d()
1638 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea; in si_surface_init_2d()
1645 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in si_surface_init_2d()
1653 for (i = start_level; i <= surf->last_level; i++) { in si_surface_init_2d()
1655 … si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset); in si_surface_init_2d()
1674 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in si_surface_init_2d()
1677 aligned_offset = offset = surf->bo_size; in si_surface_init_2d()
1679 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); in si_surface_init_2d()
1681 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in si_surface_init_2d()
1682 if (surf->level == level) { in si_surface_init_2d()
1683 surf->tiling_index[i] = tile_mode; in si_surface_init_2d()
1685 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_2d()
1687 surf->stencil_tiling_index[i] = tile_mode; in si_surface_init_2d()
1695 struct radeon_surface *surf, in si_surface_init_2d_miptrees() argument
1706 …r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, su… in si_surface_init_2d_miptrees()
1711 if (surf->flags & RADEON_SURF_SBUFFER) { in si_surface_init_2d_miptrees()
1712 …surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_banks, s… in si_surface_init_2d_miptrees()
1713 surf->stencil_offset = surf->stencil_level[0].offset; in si_surface_init_2d_miptrees()
1719 struct radeon_surface *surf) in si_surface_init() argument
1725 if (surf->nsamples > 1) { in si_surface_init()
1726 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_init()
1727 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in si_surface_init()
1731 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in si_surface_init()
1733 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in si_surface_init()
1741 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_init()
1742 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in si_surface_init()
1747 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_init()
1752 surf->stencil_offset = 0; in si_surface_init()
1753 surf->bo_alignment = 0; in si_surface_init()
1758 r = r6_surface_init_linear(surf_man, surf, 0, 0); in si_surface_init()
1761 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in si_surface_init()
1764 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1767 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1779 struct radeon_surface *surf) in si_surface_best() argument
1784 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in si_surface_best()
1786 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) && in si_surface_best()
1787 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) { in si_surface_best()
1789 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in si_surface_best()
1790 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in si_surface_best()
1793 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_best()
2110 struct radeon_surface *surf, in cik_surface_sanity() argument
2114 if (surf->npix_x > 16384 || surf->npix_y > 16384 || surf->npix_z > 16384) { in cik_surface_sanity()
2119 if (surf->last_level > 15) { in cik_surface_sanity()
2125 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in cik_surface_sanity()
2126 if (surf->nsamples > 1) { in cik_surface_sanity()
2131 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_sanity()
2132 surf->flags |= RADEON_SURF_SET(mode, MODE); in cik_surface_sanity()
2135 if (surf->nsamples > 1 && mode != RADEON_SURF_MODE_2D) { in cik_surface_sanity()
2139 if (!surf->tile_split) { in cik_surface_sanity()
2141 surf->mtilea = 1; in cik_surface_sanity()
2142 surf->bankw = 1; in cik_surface_sanity()
2143 surf->bankh = 1; in cik_surface_sanity()
2144 surf->tile_split = 64; in cik_surface_sanity()
2145 surf->stencil_tile_split = 64; in cik_surface_sanity()
2150 if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) { in cik_surface_sanity()
2151 switch (surf->nsamples) { in cik_surface_sanity()
2166 if (surf->flags & RADEON_SURF_SBUFFER) { in cik_surface_sanity()
2169 cik_get_2d_params(surf_man, 1, surf->nsamples, false, in cik_surface_sanity()
2171 &surf->stencil_tile_split, in cik_surface_sanity()
2174 } else if (surf->flags & RADEON_SURF_SCANOUT) { in cik_surface_sanity()
2181 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_sanity()
2182 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), *tile_mode, in cik_surface_sanity()
2183 NULL, &surf->tile_split, NULL, &surf->mtilea, in cik_surface_sanity()
2184 &surf->bankw, &surf->bankh); in cik_surface_sanity()
2188 if (surf->flags & RADEON_SURF_SBUFFER) { in cik_surface_sanity()
2191 if (surf->flags & RADEON_SURF_ZBUFFER) { in cik_surface_sanity()
2193 } else if (surf->flags & RADEON_SURF_SCANOUT) { in cik_surface_sanity()
2208 struct radeon_surface *surf, in cik_surface_init_2d() argument
2229 tileb = surf->nsamples * tileb_1x; in cik_surface_init_2d()
2239 mtilew = (tilew * surf->bankw * num_pipes) * surf->mtilea; in cik_surface_init_2d()
2240 mtileh = (tileh * surf->bankh * num_banks) / surf->mtilea; in cik_surface_init_2d()
2247 surf->bo_alignment = MAX2(surf->bo_alignment, alignment); in cik_surface_init_2d()
2255 for (i = start_level; i <= surf->last_level; i++) { in cik_surface_init_2d()
2257 … si_surf_minify_2d(surf, level+i, bpe, i, slice_pt, mtilew, mtileh, 1, mtileb, aligned_offset); in cik_surface_init_2d()
2276 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in cik_surface_init_2d()
2279 aligned_offset = offset = surf->bo_size; in cik_surface_init_2d()
2281 aligned_offset = ALIGN(aligned_offset, surf->bo_alignment); in cik_surface_init_2d()
2283 if (surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX) { in cik_surface_init_2d()
2284 if (surf->level == level) { in cik_surface_init_2d()
2285 surf->tiling_index[i] = tile_mode; in cik_surface_init_2d()
2287 surf->stencil_tiling_index[i] = tile_mode; in cik_surface_init_2d()
2289 surf->stencil_tiling_index[i] = tile_mode; in cik_surface_init_2d()
2297 struct radeon_surface *surf, in cik_surface_init_2d_miptrees() argument
2303 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_init_2d_miptrees()
2304 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER), tile_mode, in cik_surface_init_2d_miptrees()
2307 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, in cik_surface_init_2d_miptrees()
2308 surf->tile_split, num_pipes, num_banks, 0, 0); in cik_surface_init_2d_miptrees()
2313 if (surf->flags & RADEON_SURF_SBUFFER) { in cik_surface_init_2d_miptrees()
2314 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, in cik_surface_init_2d_miptrees()
2315 surf->stencil_tile_split, num_pipes, num_banks, in cik_surface_init_2d_miptrees()
2316 surf->bo_size, 0); in cik_surface_init_2d_miptrees()
2317 surf->stencil_offset = surf->stencil_level[0].offset; in cik_surface_init_2d_miptrees()
2323 struct radeon_surface *surf) in cik_surface_init() argument
2329 if (surf->nsamples > 1) { in cik_surface_init()
2330 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_init()
2331 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE); in cik_surface_init()
2335 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in cik_surface_init()
2337 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER)) { in cik_surface_init()
2345 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_init()
2346 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in cik_surface_init()
2351 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_init()
2356 surf->stencil_offset = 0; in cik_surface_init()
2357 surf->bo_alignment = 0; in cik_surface_init()
2362 r = r6_surface_init_linear(surf_man, surf, 0, 0); in cik_surface_init()
2365 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in cik_surface_init()
2368 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2371 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2383 struct radeon_surface *surf) in cik_surface_best() argument
2388 mode = (surf->flags >> RADEON_SURF_MODE_SHIFT) & RADEON_SURF_MODE_MASK; in cik_surface_best()
2390 if (surf->flags & (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) && in cik_surface_best()
2391 !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX)) { in cik_surface_best()
2393 surf->flags = RADEON_SURF_CLR(surf->flags, MODE); in cik_surface_best()
2394 surf->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE); in cik_surface_best()
2397 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_best()
2460 struct radeon_surface *surf, in radeon_surface_sanity() argument
2464 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) { in radeon_surface_sanity()
2469 if (!surf->npix_x || !surf->npix_y || !surf->npix_z) { in radeon_surface_sanity()
2472 if (!surf->blk_w || !surf->blk_h || !surf->blk_d) { in radeon_surface_sanity()
2475 if (!surf->array_size) { in radeon_surface_sanity()
2479 surf->array_size = next_power_of_two(surf->array_size); in radeon_surface_sanity()
2481 switch (surf->nsamples) { in radeon_surface_sanity()
2493 if (surf->npix_y > 1) { in radeon_surface_sanity()
2497 if (surf->npix_z > 1) { in radeon_surface_sanity()
2502 if (surf->npix_z > 1) { in radeon_surface_sanity()
2507 surf->array_size = 8; in radeon_surface_sanity()
2509 surf->array_size = 6; in radeon_surface_sanity()
2515 if (surf->npix_y > 1) { in radeon_surface_sanity()
2528 struct radeon_surface *surf) in radeon_surface_init() argument
2533 type = RADEON_SURF_GET(surf->flags, TYPE); in radeon_surface_init()
2534 mode = RADEON_SURF_GET(surf->flags, MODE); in radeon_surface_init()
2536 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_init()
2540 return surf_man->surface_init(surf_man, surf); in radeon_surface_init()
2545 struct radeon_surface *surf) in radeon_surface_best() argument
2550 type = RADEON_SURF_GET(surf->flags, TYPE); in radeon_surface_best()
2551 mode = RADEON_SURF_GET(surf->flags, MODE); in radeon_surface_best()
2553 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_best()
2557 return surf_man->surface_best(surf_man, surf); in radeon_surface_best()