Lines Matching refs:surf_man
90 typedef int (*hw_init_surface_t)(struct radeon_surface_manager *surf_man,
92 typedef int (*hw_best_surface_t)(struct radeon_surface_manager *surf_man,
132 static int radeon_get_family(struct radeon_surface_manager *surf_man) in radeon_get_family() argument
134 switch (surf_man->device_id) { in radeon_get_family()
135 #define CHIPSET(pci_id, name, fam) case pci_id: surf_man->family = CHIP_##fam; break; in radeon_get_family()
195 static int r6_init_hw_info(struct radeon_surface_manager *surf_man) in r6_init_hw_info() argument
201 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in r6_init_hw_info()
207 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
208 version = drmGetVersion(surf_man->fd); in r6_init_hw_info()
210 surf_man->hw_info.allow_2d = 1; in r6_init_hw_info()
216 surf_man->hw_info.num_pipes = 1; in r6_init_hw_info()
219 surf_man->hw_info.num_pipes = 2; in r6_init_hw_info()
222 surf_man->hw_info.num_pipes = 4; in r6_init_hw_info()
225 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
228 surf_man->hw_info.num_pipes = 8; in r6_init_hw_info()
229 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
235 surf_man->hw_info.num_banks = 4; in r6_init_hw_info()
238 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
241 surf_man->hw_info.num_banks = 8; in r6_init_hw_info()
242 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
248 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
251 surf_man->hw_info.group_bytes = 512; in r6_init_hw_info()
254 surf_man->hw_info.group_bytes = 256; in r6_init_hw_info()
255 surf_man->hw_info.allow_2d = 0; in r6_init_hw_info()
261 static int r6_surface_init_linear(struct radeon_surface_manager *surf_man, in r6_surface_init_linear() argument
270 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear()
275 xalign = MAX2(1, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear()
295 static int r6_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, in r6_surface_init_linear_aligned() argument
304 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_linear_aligned()
306 xalign = MAX2(64, surf_man->hw_info.group_bytes / surf->bpe); in r6_surface_init_linear_aligned()
323 static int r6_surface_init_1d(struct radeon_surface_manager *surf_man, in r6_surface_init_1d() argument
332 xalign = surf_man->hw_info.group_bytes / (tilew * surf->bpe * surf->nsamples); in r6_surface_init_1d()
340 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in r6_surface_init_1d()
356 static int r6_surface_init_2d(struct radeon_surface_manager *surf_man, in r6_surface_init_2d() argument
366 xalign = (surf_man->hw_info.group_bytes * surf_man->hw_info.num_banks) / in r6_surface_init_2d()
368 xalign = MAX2(tilew * surf_man->hw_info.num_banks, xalign); in r6_surface_init_2d()
371 yalign = tilew * surf_man->hw_info.num_pipes; in r6_surface_init_2d()
377 MAX2(surf_man->hw_info.num_pipes * in r6_surface_init_2d()
378 surf_man->hw_info.num_banks * in r6_surface_init_2d()
388 return r6_surface_init_1d(surf_man, surf, offset, i); in r6_surface_init_2d()
399 static int r6_surface_init(struct radeon_surface_manager *surf_man, in r6_surface_init() argument
429 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in r6_surface_init()
452 r = r6_surface_init_linear(surf_man, surf, 0, 0); in r6_surface_init()
455 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in r6_surface_init()
458 r = r6_surface_init_1d(surf_man, surf, 0, 0); in r6_surface_init()
461 r = r6_surface_init_2d(surf_man, surf, 0, 0); in r6_surface_init()
469 static int r6_surface_best(struct radeon_surface_manager *surf_man, in r6_surface_best() argument
480 static int eg_init_hw_info(struct radeon_surface_manager *surf_man) in eg_init_hw_info() argument
486 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in eg_init_hw_info()
492 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
493 version = drmGetVersion(surf_man->fd); in eg_init_hw_info()
495 surf_man->hw_info.allow_2d = 1; in eg_init_hw_info()
501 surf_man->hw_info.num_pipes = 1; in eg_init_hw_info()
504 surf_man->hw_info.num_pipes = 2; in eg_init_hw_info()
507 surf_man->hw_info.num_pipes = 4; in eg_init_hw_info()
510 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
513 surf_man->hw_info.num_pipes = 8; in eg_init_hw_info()
514 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
520 surf_man->hw_info.num_banks = 4; in eg_init_hw_info()
523 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
526 surf_man->hw_info.num_banks = 16; in eg_init_hw_info()
529 surf_man->hw_info.num_banks = 8; in eg_init_hw_info()
530 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
536 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
539 surf_man->hw_info.group_bytes = 512; in eg_init_hw_info()
542 surf_man->hw_info.group_bytes = 256; in eg_init_hw_info()
543 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
549 surf_man->hw_info.row_size = 1024; in eg_init_hw_info()
552 surf_man->hw_info.row_size = 2048; in eg_init_hw_info()
555 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
558 surf_man->hw_info.row_size = 4096; in eg_init_hw_info()
559 surf_man->hw_info.allow_2d = 0; in eg_init_hw_info()
606 static int eg_surface_init_1d(struct radeon_surface_manager *surf_man, in eg_surface_init_1d() argument
617 xalign = surf_man->hw_info.group_bytes / (tilew * bpe * surf->nsamples); in eg_surface_init_1d()
626 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in eg_surface_init_1d()
647 static int eg_surface_init_2d(struct radeon_surface_manager *surf_man, in eg_surface_init_2d() argument
670 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea; in eg_surface_init_2d()
671 mtileh = (tileh * surf->bankh * surf_man->hw_info.num_banks) / surf->mtilea; in eg_surface_init_2d()
689 return eg_surface_init_1d(surf_man, surf, level, bpe, offset, i); in eg_surface_init_2d()
700 static int eg_surface_sanity(struct radeon_surface_manager *surf_man, in eg_surface_sanity() argument
717 if (!surf_man->hw_info.allow_2d && mode > RADEON_SURF_MODE_1D) { in eg_surface_sanity()
751 if (surf_man->hw_info.num_banks < surf->mtilea) { in eg_surface_sanity()
775 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) { in eg_surface_sanity()
783 static int eg_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, in eg_surface_init_1d_miptrees() argument
793 r = eg_surface_init_1d(surf_man, surf, surf->level, surf->bpe, 0, 0); in eg_surface_init_1d_miptrees()
798 r = eg_surface_init_1d(surf_man, surf, stencil_level, 1, in eg_surface_init_1d_miptrees()
805 static int eg_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in eg_surface_init_2d_miptrees() argument
815 r = eg_surface_init_2d(surf_man, surf, surf->level, surf->bpe, in eg_surface_init_2d_miptrees()
821 r = eg_surface_init_2d(surf_man, surf, stencil_level, 1, in eg_surface_init_2d_miptrees()
828 static int eg_surface_init(struct radeon_surface_manager *surf_man, in eg_surface_init() argument
857 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_init()
868 r = r6_surface_init_linear(surf_man, surf, 0, 0); in eg_surface_init()
871 r = r6_surface_init_linear_aligned(surf_man, surf, 0, 0); in eg_surface_init()
874 r = eg_surface_init_1d_miptrees(surf_man, surf); in eg_surface_init()
877 r = eg_surface_init_2d_miptrees(surf_man, surf); in eg_surface_init()
903 static int eg_surface_best(struct radeon_surface_manager *surf_man, in eg_surface_best() argument
916 surf->mtilea = surf_man->hw_info.num_banks; in eg_surface_best()
919 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
927 r = eg_surface_sanity(surf_man, surf, mode); in eg_surface_best()
967 surf->tile_split = surf_man->hw_info.row_size; in eg_surface_best()
968 surf->stencil_tile_split = surf_man->hw_info.row_size / 2; in eg_surface_best()
1006 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) { in eg_surface_best()
1011 h_over_w = (((surf->bankh * surf_man->hw_info.num_banks) << 16) / in eg_surface_best()
1012 (surf->bankw * surf_man->hw_info.num_pipes)) >> 16; in eg_surface_best()
1192 static int si_init_hw_info(struct radeon_surface_manager *surf_man) in si_init_hw_info() argument
1198 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in si_init_hw_info()
1204 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1205 version = drmGetVersion(surf_man->fd); in si_init_hw_info()
1207 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in si_init_hw_info()
1208 surf_man->hw_info.allow_2d = 1; in si_init_hw_info()
1215 surf_man->hw_info.num_pipes = 1; in si_init_hw_info()
1218 surf_man->hw_info.num_pipes = 2; in si_init_hw_info()
1221 surf_man->hw_info.num_pipes = 4; in si_init_hw_info()
1224 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1227 surf_man->hw_info.num_pipes = 8; in si_init_hw_info()
1228 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1234 surf_man->hw_info.num_banks = 4; in si_init_hw_info()
1237 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1240 surf_man->hw_info.num_banks = 16; in si_init_hw_info()
1243 surf_man->hw_info.num_banks = 8; in si_init_hw_info()
1244 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1250 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1253 surf_man->hw_info.group_bytes = 512; in si_init_hw_info()
1256 surf_man->hw_info.group_bytes = 256; in si_init_hw_info()
1257 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1263 surf_man->hw_info.row_size = 1024; in si_init_hw_info()
1266 surf_man->hw_info.row_size = 2048; in si_init_hw_info()
1269 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1272 surf_man->hw_info.row_size = 4096; in si_init_hw_info()
1273 surf_man->hw_info.allow_2d = 0; in si_init_hw_info()
1279 static int si_surface_sanity(struct radeon_surface_manager *surf_man, in si_surface_sanity() argument
1297 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in si_surface_sanity()
1340 gb_tile_mode = surf_man->hw_info.tile_mode_array[*stencil_tile_mode]; in si_surface_sanity()
1391 gb_tile_mode = surf_man->hw_info.tile_mode_array[*tile_mode]; in si_surface_sanity()
1510 static int si_surface_init_linear_aligned(struct radeon_surface_manager *surf_man, in si_surface_init_linear_aligned() argument
1520 surf->bo_alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1525 slice_align = MAX2(64 * surf->bpe, surf_man->hw_info.group_bytes); in si_surface_init_linear_aligned()
1543 static int si_surface_init_1d(struct radeon_surface_manager *surf_man, in si_surface_init_1d() argument
1550 unsigned alignment = MAX2(256, surf_man->hw_info.group_bytes); in si_surface_init_1d()
1557 slice_align = surf_man->hw_info.group_bytes; in si_surface_init_1d()
1592 static int si_surface_init_1d_miptrees(struct radeon_surface_manager *surf_man, in si_surface_init_1d_miptrees() argument
1598 r = si_surface_init_1d(surf_man, surf, surf->level, surf->bpe, tile_mode, 0, 0); in si_surface_init_1d_miptrees()
1604 …r = si_surface_init_1d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, surf->bo_size, 0… in si_surface_init_1d_miptrees()
1610 static int si_surface_init_2d(struct radeon_surface_manager *surf_man, in si_surface_init_2d() argument
1674 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in si_surface_init_2d()
1694 static int si_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in si_surface_init_2d_miptrees() argument
1703 gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in si_surface_init_2d_miptrees()
1706 …r = si_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, num_pipes, num_banks, su… in si_surface_init_2d_miptrees()
1712 …r = si_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, num_pipes, num_b… in si_surface_init_2d_miptrees()
1718 static int si_surface_init(struct radeon_surface_manager *surf_man, in si_surface_init() argument
1747 r = si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_init()
1758 r = r6_surface_init_linear(surf_man, surf, 0, 0); in si_surface_init()
1761 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in si_surface_init()
1764 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1767 r = si_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in si_surface_init()
1778 static int si_surface_best(struct radeon_surface_manager *surf_man, in si_surface_best() argument
1793 return si_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in si_surface_best()
1850 static void cik_get_2d_params(struct radeon_surface_manager *surf_man, in cik_get_2d_params() argument
1860 uint32_t gb_tile_mode = surf_man->hw_info.tile_mode_array[tile_mode]; in cik_get_2d_params()
1938 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_get_2d_params()
1946 gb_macrotile_mode = surf_man->hw_info.macrotile_mode_array[macrotile_index]; in cik_get_2d_params()
2021 static int cik_init_hw_info(struct radeon_surface_manager *surf_man) in cik_init_hw_info() argument
2027 r = radeon_get_value(surf_man->fd, RADEON_INFO_TILING_CONFIG, in cik_init_hw_info()
2033 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2034 version = drmGetVersion(surf_man->fd); in cik_init_hw_info()
2036 …if (!radeon_get_value(surf_man->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, surf_man->hw_info.tile_mode_ar… in cik_init_hw_info()
2037 …!radeon_get_value(surf_man->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, surf_man->hw_info.macrotile_… in cik_init_hw_info()
2038 surf_man->hw_info.allow_2d = 1; in cik_init_hw_info()
2045 surf_man->hw_info.num_pipes = 1; in cik_init_hw_info()
2048 surf_man->hw_info.num_pipes = 2; in cik_init_hw_info()
2051 surf_man->hw_info.num_pipes = 4; in cik_init_hw_info()
2054 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2057 surf_man->hw_info.num_pipes = 8; in cik_init_hw_info()
2058 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2064 surf_man->hw_info.num_banks = 4; in cik_init_hw_info()
2067 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2070 surf_man->hw_info.num_banks = 16; in cik_init_hw_info()
2073 surf_man->hw_info.num_banks = 8; in cik_init_hw_info()
2074 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2080 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2083 surf_man->hw_info.group_bytes = 512; in cik_init_hw_info()
2086 surf_man->hw_info.group_bytes = 256; in cik_init_hw_info()
2087 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2093 surf_man->hw_info.row_size = 1024; in cik_init_hw_info()
2096 surf_man->hw_info.row_size = 2048; in cik_init_hw_info()
2099 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2102 surf_man->hw_info.row_size = 4096; in cik_init_hw_info()
2103 surf_man->hw_info.allow_2d = 0; in cik_init_hw_info()
2109 static int cik_surface_sanity(struct radeon_surface_manager *surf_man, in cik_surface_sanity() argument
2125 (!surf_man->hw_info.allow_2d || !(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))) { in cik_surface_sanity()
2169 cik_get_2d_params(surf_man, 1, surf->nsamples, false, in cik_surface_sanity()
2181 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_sanity()
2207 static int cik_surface_init_2d(struct radeon_surface_manager *surf_man, in cik_surface_init_2d() argument
2227 tile_split = MIN2(surf_man->hw_info.row_size, tile_split); in cik_surface_init_2d()
2276 return si_surface_init_1d(surf_man, surf, level, bpe, tile_mode, offset, i); in cik_surface_init_2d()
2296 static int cik_surface_init_2d_miptrees(struct radeon_surface_manager *surf_man, in cik_surface_init_2d_miptrees() argument
2303 cik_get_2d_params(surf_man, surf->bpe, surf->nsamples, in cik_surface_init_2d_miptrees()
2307 r = cik_surface_init_2d(surf_man, surf, surf->level, surf->bpe, tile_mode, in cik_surface_init_2d_miptrees()
2314 r = cik_surface_init_2d(surf_man, surf, surf->stencil_level, 1, stencil_tile_mode, in cik_surface_init_2d_miptrees()
2322 static int cik_surface_init(struct radeon_surface_manager *surf_man, in cik_surface_init() argument
2351 r = cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_init()
2362 r = r6_surface_init_linear(surf_man, surf, 0, 0); in cik_surface_init()
2365 r = si_surface_init_linear_aligned(surf_man, surf, tile_mode, 0, 0); in cik_surface_init()
2368 r = si_surface_init_1d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2371 r = cik_surface_init_2d_miptrees(surf_man, surf, tile_mode, stencil_tile_mode); in cik_surface_init()
2382 static int cik_surface_best(struct radeon_surface_manager *surf_man, in cik_surface_best() argument
2397 return cik_surface_sanity(surf_man, surf, mode, &tile_mode, &stencil_tile_mode); in cik_surface_best()
2407 struct radeon_surface_manager *surf_man; in radeon_surface_manager_new() local
2409 surf_man = calloc(1, sizeof(struct radeon_surface_manager)); in radeon_surface_manager_new()
2410 if (surf_man == NULL) { in radeon_surface_manager_new()
2413 surf_man->fd = fd; in radeon_surface_manager_new()
2414 if (radeon_get_value(fd, RADEON_INFO_DEVICE_ID, &surf_man->device_id)) { in radeon_surface_manager_new()
2417 if (radeon_get_family(surf_man)) { in radeon_surface_manager_new()
2421 if (surf_man->family <= CHIP_RV740) { in radeon_surface_manager_new()
2422 if (r6_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2425 surf_man->surface_init = &r6_surface_init; in radeon_surface_manager_new()
2426 surf_man->surface_best = &r6_surface_best; in radeon_surface_manager_new()
2427 } else if (surf_man->family <= CHIP_ARUBA) { in radeon_surface_manager_new()
2428 if (eg_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2431 surf_man->surface_init = &eg_surface_init; in radeon_surface_manager_new()
2432 surf_man->surface_best = &eg_surface_best; in radeon_surface_manager_new()
2433 } else if (surf_man->family < CHIP_BONAIRE) { in radeon_surface_manager_new()
2434 if (si_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2437 surf_man->surface_init = &si_surface_init; in radeon_surface_manager_new()
2438 surf_man->surface_best = &si_surface_best; in radeon_surface_manager_new()
2440 if (cik_init_hw_info(surf_man)) { in radeon_surface_manager_new()
2443 surf_man->surface_init = &cik_surface_init; in radeon_surface_manager_new()
2444 surf_man->surface_best = &cik_surface_best; in radeon_surface_manager_new()
2447 return surf_man; in radeon_surface_manager_new()
2449 free(surf_man); in radeon_surface_manager_new()
2454 radeon_surface_manager_free(struct radeon_surface_manager *surf_man) in radeon_surface_manager_free() argument
2456 free(surf_man); in radeon_surface_manager_free()
2459 static int radeon_surface_sanity(struct radeon_surface_manager *surf_man, in radeon_surface_sanity() argument
2464 if (surf_man == NULL || surf_man->surface_init == NULL || surf == NULL) { in radeon_surface_sanity()
2506 if (surf_man->family >= CHIP_RV770) { in radeon_surface_sanity()
2527 radeon_surface_init(struct radeon_surface_manager *surf_man, in radeon_surface_init() argument
2536 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_init()
2540 return surf_man->surface_init(surf_man, surf); in radeon_surface_init()
2544 radeon_surface_best(struct radeon_surface_manager *surf_man, in radeon_surface_best() argument
2553 r = radeon_surface_sanity(surf_man, surf, type, mode); in radeon_surface_best()
2557 return surf_man->surface_best(surf_man, surf); in radeon_surface_best()