80                const TargetRegisterInfo *TRI);
90                            const TargetRegisterInfo *TRI);
120   void print(const MachineOperand &Op, const TargetRegisterInfo *TRI,
124   void print(const MCCFIInstruction &CFI, const TargetRegisterInfo *TRI);
147                      const TargetRegisterInfo *TRI) {  in printReg()  argument
153   else if (Reg < TRI->getNumRegs())  in printReg()
154     OS << '%' << StringRef(TRI->getName(Reg)).lower();  in printReg()
160                      const TargetRegisterInfo *TRI) {  in printReg()  argument
162   printReg(Reg, OS, TRI);  in printReg()
199                          const TargetRegisterInfo *TRI) {  in convert()  argument
210         StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();  in convert()
213       printReg(PreferredReg, VReg.PreferredRegister, TRI);  in convert()
220     printReg(I->first, LiveIn.Register, TRI);  in convert()
222       printReg(I->second, LiveIn.VirtualRegister, TRI);  in convert()
234       printReg(I, Reg, TRI);  in convert()
273                                      const TargetRegisterInfo *TRI) {  in convertStackObjects()  argument
322     printReg(CSInfo.getReg(), Reg, TRI);  in convertStackObjects()
414   const auto *TRI = MF.getSubtarget().getRegisterInfo();  in initRegisterMaskIds()  local
416   for (const uint32_t *Mask : TRI->getRegMasks())  in initRegisterMaskIds()
472   const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo();  in print()  local
473   assert(TRI && "Expected target register info");  in print()
481       printReg(LI.PhysReg, OS, TRI);  in print()
529   const auto *TRI = SubTarget.getRegisterInfo();  in print()  local
530   assert(TRI && "Expected target register info");  in print()
543     print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies, /*IsDef=*/true);  in print()
558     print(MI.getOperand(I), TRI, I, ShouldPrintRegisterTies);  in print()
729 void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI,  in print()  argument
751     printReg(Op.getReg(), OS, TRI);  in print()
754       OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());  in print()
812       OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();  in print()
821     for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {  in print()
825         printReg(Reg, OS, TRI);  in print()
840     print(MMI.getFrameInstructions()[Op.getCFIIndex()], TRI);  in print()
920                              const TargetRegisterInfo *TRI) {  in printCFIRegister()  argument
921   int Reg = TRI->getLLVMRegNum(DwarfReg, true);  in printCFIRegister()
926   printReg(Reg, OS, TRI);  in printCFIRegister()
930                       const TargetRegisterInfo *TRI) {  in print()  argument
936     printCFIRegister(CFI.getRegister(), OS, TRI);  in print()
942     printCFIRegister(CFI.getRegister(), OS, TRI);  in print()
949     printCFIRegister(CFI.getRegister(), OS, TRI);  in print()
961     printCFIRegister(CFI.getRegister(), OS, TRI);  in print()