Lines Matching refs:MO
263 hash_code llvm::hash_value(const MachineOperand &MO) { in hash_value() argument
264 switch (MO.getType()) { in hash_value()
267 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef()); in hash_value()
269 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm()); in hash_value()
271 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm()); in hash_value()
273 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm()); in hash_value()
275 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB()); in hash_value()
277 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); in hash_value()
280 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(), in hash_value()
281 MO.getOffset()); in hash_value()
283 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex()); in hash_value()
285 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(), in hash_value()
286 MO.getSymbolName()); in hash_value()
288 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(), in hash_value()
289 MO.getOffset()); in hash_value()
291 return hash_combine(MO.getType(), MO.getTargetFlags(), in hash_value()
292 MO.getBlockAddress(), MO.getOffset()); in hash_value()
295 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask()); in hash_value()
297 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata()); in hash_value()
299 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol()); in hash_value()
301 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex()); in hash_value()
677 for (const MachineOperand &MO : MI.operands()) in MachineInstr() local
678 addOperand(MF, MO); in MachineInstr()
697 for (MachineOperand &MO : operands()) in RemoveRegOperandsFromUseLists()
698 if (MO.isReg()) in RemoveRegOperandsFromUseLists()
699 MRI.removeRegOperandFromUseList(&MO); in RemoveRegOperandsFromUseLists()
706 for (MachineOperand &MO : operands()) in AddRegOperandsToUseLists()
707 if (MO.isReg()) in AddRegOperandsToUseLists()
708 MRI.addRegOperandToUseList(&MO); in AddRegOperandsToUseLists()
857 MachineMemOperand *MO) { in addMemOperand() argument
865 NewMemRefs[NewNum - 1] = MO; in addMemOperand()
908 const MachineOperand &MO = getOperand(i); in isIdenticalTo() local
910 if (!MO.isReg()) { in isIdenticalTo()
911 if (!MO.isIdenticalTo(OMO)) in isIdenticalTo()
919 if (MO.isDef()) { in isIdenticalTo()
923 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) || in isIdenticalTo()
925 if (MO.getReg() != OMO.getReg()) in isIdenticalTo()
928 if (!MO.isIdenticalTo(OMO)) in isIdenticalTo()
930 if (Check == CheckKillDead && MO.isDead() != OMO.isDead()) in isIdenticalTo()
934 if (!MO.isIdenticalTo(OMO)) in isIdenticalTo()
936 if (Check == CheckKillDead && MO.isKill() != OMO.isKill()) in isIdenticalTo()
972 for (const MachineOperand &MO : MI->operands()) { in eraseFromParentAndMarkDBGValuesForRemoval() local
973 if (!MO.isReg() || !MO.isDef()) in eraseFromParentAndMarkDBGValuesForRemoval()
975 unsigned Reg = MO.getReg(); in eraseFromParentAndMarkDBGValuesForRemoval()
996 const MachineOperand &MO = getOperand(i); in getNumExplicitOperands() local
997 if (!MO.isReg() || !MO.isImplicit()) in getNumExplicitOperands()
1141 const MachineOperand &MO = getOperand(OpIdx); in getRegClassConstraintEffectForVRegImpl() local
1142 if (!MO.isReg() || MO.getReg() != Reg) in getRegClassConstraintEffectForVRegImpl()
1152 const MachineOperand &MO = getOperand(OpIdx); in getRegClassConstraintEffect() local
1153 assert(MO.isReg() && in getRegClassConstraintEffect()
1156 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect()
1182 const MachineOperand &MO = getOperand(i); in findRegisterUseOperandIdx() local
1183 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1185 unsigned MOReg = MO.getReg(); in findRegisterUseOperandIdx()
1193 if (!isKill || MO.isKill()) in findRegisterUseOperandIdx()
1210 const MachineOperand &MO = getOperand(i); in readsWritesVirtualRegister() local
1211 if (!MO.isReg() || MO.getReg() != Reg) in readsWritesVirtualRegister()
1215 if (MO.isUse()) in readsWritesVirtualRegister()
1216 Use |= !MO.isUndef(); in readsWritesVirtualRegister()
1217 else if (MO.getSubReg() && !MO.isUndef()) in readsWritesVirtualRegister()
1236 const MachineOperand &MO = getOperand(i); in findRegisterDefOperandIdx() local
1239 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg)) in findRegisterDefOperandIdx()
1241 if (!MO.isReg() || !MO.isDef()) in findRegisterDefOperandIdx()
1243 unsigned MOReg = MO.getReg(); in findRegisterDefOperandIdx()
1252 if (Found && (!isDead || MO.isDead())) in findRegisterDefOperandIdx()
1317 const MachineOperand &MO = getOperand(OpIdx); in findTiedOperandIdx() local
1318 assert(MO.isTied() && "Operand isn't tied"); in findTiedOperandIdx()
1321 if (MO.TiedTo < TiedMax) in findTiedOperandIdx()
1322 return MO.TiedTo - 1; in findTiedOperandIdx()
1327 if (MO.isUse()) in findTiedOperandIdx()
1374 for (MachineOperand &MO : operands()) { in clearKillInfo()
1375 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1376 MO.setIsKill(false); in clearKillInfo()
1387 for (MachineOperand &MO : operands()) { in substituteRegister()
1388 if (!MO.isReg() || MO.getReg() != FromReg) in substituteRegister()
1390 MO.substPhysReg(ToReg, RegInfo); in substituteRegister()
1393 for (MachineOperand &MO : operands()) { in substituteRegister()
1394 if (!MO.isReg() || MO.getReg() != FromReg) in substituteRegister()
1396 MO.substVirtReg(ToReg, SubIdx, RegInfo); in substituteRegister()
1538 for (const MachineOperand &MO : operands()) { in allDefsAreDead() local
1539 if (!MO.isReg() || MO.isUse()) in allDefsAreDead()
1541 if (!MO.isDead()) in allDefsAreDead()
1553 const MachineOperand &MO = MI->getOperand(i); in copyImplicitOps() local
1554 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) in copyImplicitOps()
1555 addOperand(MF, MO); in copyImplicitOps()
1650 const MachineOperand &MO = getOperand(i); in print() local
1652 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) in print()
1653 VirtRegs.push_back(MO.getReg()); in print()
1660 MO.isReg() && MO.isImplicit() && MO.isDef()) { in print()
1661 unsigned Reg = MO.getReg(); in print()
1689 if (isDebugValue() && MO.isMetadata()) { in print()
1691 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata()); in print()
1695 MO.print(OS, MST, TRI); in print()
1696 } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) { in print()
1697 OS << TRI->getSubRegIndexName(MO.getImm()); in print()
1698 } else if (i == AsmDescOp && MO.isImm()) { in print()
1701 unsigned Flag = MO.getImm(); in print()
1729 MO.print(OS, MST, TRI); in print()
1815 MachineOperand &MO = getOperand(i); in addRegisterKilled() local
1816 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) in addRegisterKilled()
1818 unsigned Reg = MO.getReg(); in addRegisterKilled()
1824 if (MO.isKill()) in addRegisterKilled()
1830 MO.setIsKill(); in addRegisterKilled()
1833 } else if (hasAliases && MO.isKill() && in addRegisterKilled()
1869 for (MachineOperand &MO : operands()) { in clearRegisterKills()
1870 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in clearRegisterKills()
1872 unsigned OpReg = MO.getReg(); in clearRegisterKills()
1874 MO.setIsKill(false); in clearRegisterKills()
1887 MachineOperand &MO = getOperand(i); in addRegisterDead() local
1888 if (!MO.isReg() || !MO.isDef()) in addRegisterDead()
1890 unsigned MOReg = MO.getReg(); in addRegisterDead()
1895 MO.setIsDead(); in addRegisterDead()
1897 } else if (hasAliases && MO.isDead() && in addRegisterDead()
1931 for (MachineOperand &MO : operands()) { in clearRegisterDeads()
1932 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg) in clearRegisterDeads()
1934 MO.setIsDead(false); in clearRegisterDeads()
1939 for (MachineOperand &MO : operands()) { in setRegisterDefReadUndef()
1940 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0) in setRegisterDefReadUndef()
1942 MO.setIsUndef(IsUndef); in setRegisterDefReadUndef()
1949 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo); in addRegisterDefined() local
1950 if (MO) in addRegisterDefined()
1953 for (const MachineOperand &MO : operands()) { in addRegisterDefined() local
1954 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() && in addRegisterDefined()
1955 MO.getSubReg() == 0) in addRegisterDefined()
1967 for (MachineOperand &MO : operands()) { in setPhysRegsDeadExcept()
1968 if (MO.isRegMask()) { in setPhysRegsDeadExcept()
1972 if (!MO.isReg() || !MO.isDef()) continue; in setPhysRegsDeadExcept()
1973 unsigned Reg = MO.getReg(); in setPhysRegsDeadExcept()
1978 MO.setIsDead(); in setPhysRegsDeadExcept()
1995 for (const MachineOperand &MO : MI->operands()) { in getHashValue() local
1996 if (MO.isReg() && MO.isDef() && in getHashValue()
1997 TargetRegisterInfo::isVirtualRegister(MO.getReg())) in getHashValue()
2000 HashComponents.push_back(hash_value(MO)); in getHashValue()