201     void visitMachineOperand(const MachineOperand *MO, unsigned MONum);
213     void report(const char *msg, const MachineOperand *MO, unsigned MONum);
223     void checkLiveness(const MachineOperand *MO, unsigned MONum);
430                              const MachineOperand *MO, unsigned MONum) {  in report()  argument
433   errs() << "- operand " << MONum << ":   ";  in report()
832 MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {  in visitMachineOperand()  argument
837     NumDefs = (MONum == 0 && MO->isReg()) ? NumDefs : 0;  in visitMachineOperand()
840   if (MONum < NumDefs) {  in visitMachineOperand()
841     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];  in visitMachineOperand()
843       report("Explicit definition must be a register", MO, MONum);  in visitMachineOperand()
845       report("Explicit definition marked as use", MO, MONum);  in visitMachineOperand()
847       report("Explicit definition marked as implicit", MO, MONum);  in visitMachineOperand()
848   } else if (MONum < MCID.getNumOperands()) {  in visitMachineOperand()
849     const MCOperandInfo &MCOI = MCID.OpInfo[MONum];  in visitMachineOperand()
853         !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) {  in visitMachineOperand()
855         report("Explicit operand marked as def", MO, MONum);  in visitMachineOperand()
857         report("Explicit operand marked as implicit", MO, MONum);  in visitMachineOperand()
860     int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO);  in visitMachineOperand()
863         report("Tied use must be a register", MO, MONum);  in visitMachineOperand()
865         report("Operand should be tied", MO, MONum);  in visitMachineOperand()
866       else if (unsigned(TiedTo) != MI->findTiedOperandIdx(MONum))  in visitMachineOperand()
867         report("Tied def doesn't match MCInstrDesc", MO, MONum);  in visitMachineOperand()
869       report("Explicit operand should not be tied", MO, MONum);  in visitMachineOperand()
873       report("Extra explicit operand on non-variadic instruction", MO, MONum);  in visitMachineOperand()
882       checkLiveness(MO, MONum);  in visitMachineOperand()
886       unsigned OtherIdx = MI->findTiedOperandIdx(MONum);  in visitMachineOperand()
889         report("Must be tied to a register", MO, MONum);  in visitMachineOperand()
891         report("Missing tie flags on tied operand", MO, MONum);  in visitMachineOperand()
892       if (MI->findTiedOperandIdx(OtherIdx) != MONum)  in visitMachineOperand()
893         report("Inconsistent tie links", MO, MONum);  in visitMachineOperand()
894       if (MONum < MCID.getNumDefs()) {  in visitMachineOperand()
898                    MO, MONum);  in visitMachineOperand()
901             report("Explicit def should be tied to implicit use", MO, MONum);  in visitMachineOperand()
909         MI->isRegTiedToDefOperand(MONum, &DefIdx) &&  in visitMachineOperand()
911       report("Two-address instruction operands must be identical", MO, MONum);  in visitMachineOperand()
914     if (MONum < MCID.getNumOperands() && !MO->isImplicit()) {  in visitMachineOperand()
919           report("Illegal subregister index for physical register", MO, MONum);  in visitMachineOperand()
923               TII->getRegClass(MCID, MONum, TRI, *MF)) {  in visitMachineOperand()
925             report("Illegal physical register for instruction", MO, MONum);  in visitMachineOperand()
937             report("Invalid subregister index for virtual register", MO, MONum);  in visitMachineOperand()
943             report("Invalid register class for subregister index", MO, MONum);  in visitMachineOperand()
950               TII->getRegClass(MCID, MONum, TRI, *MF)) {  in visitMachineOperand()
955               report("No largest legal super class exists.", MO, MONum);  in visitMachineOperand()
960               report("No matching super-reg register class.", MO, MONum);  in visitMachineOperand()
965             report("Illegal virtual register for instruction", MO, MONum);  in visitMachineOperand()
982       report("PHI operand is not in the CFG", MO, MONum);  in visitMachineOperand()
1016         report("Instruction loads from dead spill slot", MO, MONum);  in visitMachineOperand()
1020         report("Instruction stores to dead spill slot", MO, MONum);  in visitMachineOperand()
1031 void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {  in checkLiveness()  argument
1047         report("Kill missing from LiveVariables", MO, MONum);  in checkLiveness()
1059               report("No live segment at use", MO, MONum);  in checkLiveness()
1064               report("Live range continues after kill flag", MO, MONum);  in checkLiveness()
1077             report("No live segment at use", MO, MONum);  in checkLiveness()
1083             report("Live range continues after kill flag", MO, MONum);  in checkLiveness()
1087           report("Virtual register has no live interval", MO, MONum);  in checkLiveness()
1127           report("Using an undefined physical register", MO, MONum);  in checkLiveness()
1129         report("Reading virtual register without a def", MO, MONum);  in checkLiveness()
1136           report("Using a killed virtual register", MO, MONum);  in checkLiveness()
1154       report("Multiple virtual register defs in SSA form", MO, MONum);  in checkLiveness()
1166             report("Inconsistent valno->def", MO, MONum);  in checkLiveness()
1171           report("No live segment at def", MO, MONum);  in checkLiveness()
1178             report("Live range continues after dead def flag", MO, MONum);  in checkLiveness()
1183         report("Virtual register has no Live interval", MO, MONum);  in checkLiveness()