Lines Matching refs:WriteLanes
1692 LaneBitmask WriteLanes; member
1724 Val() : Resolution(CR_Keep), WriteLanes(0), ValidLanes(0), in Val()
1728 bool isAnalyzed() const { return WriteLanes != 0; } in isAnalyzed()
1913 V.WriteLanes = ~0u; in analyzeValue()
1922 V.ValidLanes = V.WriteLanes = Lanes; in analyzeValue()
1928 V.WriteLanes = V.ValidLanes = 1; in analyzeValue()
1935 V.ValidLanes = V.WriteLanes = computeWriteLanes(DefMI, Redef); in analyzeValue()
1968 V.ValidLanes &= ~V.WriteLanes; in analyzeValue()
2048 && (V.WriteLanes & (OtherV.ValidLanes | OtherV.WriteLanes)) == 0) in analyzeValue()
2058 V.ValidLanes &= ~V.WriteLanes | OtherV.ValidLanes; in analyzeValue()
2088 if ((V.WriteLanes & OtherV.ValidLanes) == 0) in analyzeValue()
2109 if ((TRI->getSubRegIndexLaneMask(Other.SubIdx) & ~V.WriteLanes) == 0) in analyzeValue()
2157 if ((OtherV.WriteLanes & ~V.ValidLanes) != 0 && TrackSubRegLiveness) in computeAssignment()
2215 TaintedLanes &= ~OV.WriteLanes; in taintExtent()
2257 LaneBitmask TaintedLanes = V.WriteLanes & OtherV.ValidLanes; in resolveConflicts()