Lines Matching refs:FMUL
610 case ISD::FMUL: in isNegatibleForFree()
680 case ISD::FMUL: in GetNegatedExpression()
1411 case ISD::FMUL: return visitFMUL(N); in visit()
7660 if (Aggressive && N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7661 N1.getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7667 if (N0.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7675 if (N1.getOpcode() == ISD::FMUL && in visitFADDForFMACombine()
7686 if (N00.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7698 if (N10.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7711 N0.getOperand(2).getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7722 N1.getOperand(2).getOpcode() == ISD::FMUL) { in visitFADDForFMACombine()
7746 if (N020.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7772 if (N002.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7785 if (N120.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7801 if (N102.getOpcode() == ISD::FMUL) in visitFADDForFMACombine()
7842 if (N0.getOpcode() == ISD::FMUL && in visitFSUBForFMACombine()
7851 if (N1.getOpcode() == ISD::FMUL && in visitFSUBForFMACombine()
7860 N0.getOperand(0).getOpcode() == ISD::FMUL && in visitFSUBForFMACombine()
7875 if (N00.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
7889 if (N10.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
7909 if (N000.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
7931 if (N000.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
7950 N0.getOperand(2).getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
7963 N1.getOperand(2).getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
7983 if (N020.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
8006 if (N002.getOpcode() == ISD::FMUL) in visitFSUBForFMACombine()
8027 if (N120.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8054 if (N102.getOpcode() == ISD::FMUL) { in visitFSUBForFMACombine()
8084 assert(N->getOpcode() == ISD::FMUL && "Expected FMUL Operation"); in visitFMULForFMACombine()
8224 if (TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && !N0CFP && !N1CFP) { in visitFADD()
8225 if (N0.getOpcode() == ISD::FMUL) { in visitFADD()
8233 return DAG.getNode(ISD::FMUL, DL, VT, N1, NewCFP, Flags); in visitFADD()
8242 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), NewCFP, Flags); in visitFADD()
8246 if (N1.getOpcode() == ISD::FMUL) { in visitFADD()
8254 return DAG.getNode(ISD::FMUL, DL, VT, N0, NewCFP, Flags); in visitFADD()
8263 return DAG.getNode(ISD::FMUL, DL, VT, N1.getOperand(0), NewCFP, Flags); in visitFADD()
8272 return DAG.getNode(ISD::FMUL, DL, VT, in visitFADD()
8282 return DAG.getNode(ISD::FMUL, DL, VT, in visitFADD()
8293 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), in visitFADD()
8392 return DAG.getNode(ISD::FMUL, DL, VT, N0, N1, Flags); in visitFMUL()
8397 return DAG.getNode(ISD::FMUL, DL, VT, N1, N0, Flags); in visitFMUL()
8409 if (N0.getOpcode() == ISD::FMUL) { in visitFMUL()
8426 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, N01, N1, Flags); in visitFMUL()
8427 return DAG.getNode(ISD::FMUL, DL, VT, N00, MulConsts, Flags); in visitFMUL()
8440 SDValue MulConsts = DAG.getNode(ISD::FMUL, DL, VT, Two, N1, Flags); in visitFMUL()
8441 return DAG.getNode(ISD::FMUL, DL, VT, N0.getOperand(0), MulConsts, Flags); in visitFMUL()
8460 return DAG.getNode(ISD::FMUL, DL, VT, in visitFMUL()
8517 if (N2.getOpcode() == ISD::FMUL && N0 == N2.getOperand(0) && in visitFMA()
8520 return DAG.getNode(ISD::FMUL, dl, VT, N0, in visitFMA()
8526 if (N0.getOpcode() == ISD::FMUL && in visitFMA()
8531 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1), in visitFMA()
8556 return DAG.getNode(ISD::FMUL, dl, VT, N0, in visitFMA()
8564 return DAG.getNode(ISD::FMUL, dl, VT, N0, in visitFMA()
8626 SDValue NewNode = DAG.getNode(ISD::FMUL, SDLoc(U), VT, Dividend, in combineRepeatedFPDivisors()
8673 return DAG.getNode(ISD::FMUL, DL, VT, N0, in visitFDIV()
8681 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8689 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8697 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8699 } else if (N1.getOpcode() == ISD::FMUL) { in visitFDIV()
8717 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8725 return DAG.getNode(ISD::FMUL, DL, VT, N0, RV, Flags); in visitFDIV()
8779 RV = DAG.getNode(ISD::FMUL, DL, VT, N->getOperand(0), RV, &Flags); in visitFSQRT()
9212 if (N0.getOpcode() == ISD::FMUL && in visitFNEG()
9221 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), in visitFNEG()
14318 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Op, Est, Flags); in BuildReciprocalEstimate()
14324 NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); in BuildReciprocalEstimate()
14352 SDValue HalfArg = DAG.getNode(ISD::FMUL, DL, VT, ThreeHalves, Arg, Flags); in BuildRsqrtNROneConst()
14360 SDValue NewEst = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags); in BuildRsqrtNROneConst()
14363 NewEst = DAG.getNode(ISD::FMUL, DL, VT, HalfArg, NewEst, Flags); in BuildRsqrtNROneConst()
14369 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, NewEst, Flags); in BuildRsqrtNROneConst()
14390 SDValue HalfEst = DAG.getNode(ISD::FMUL, DL, VT, Est, MinusHalf, Flags); in BuildRsqrtNRTwoConst()
14393 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Est, Flags); in BuildRsqrtNRTwoConst()
14396 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, Arg, Flags); in BuildRsqrtNRTwoConst()
14402 Est = DAG.getNode(ISD::FMUL, DL, VT, Est, HalfEst, Flags); in BuildRsqrtNRTwoConst()