2017   B.RegVT = VT.getSimpleVT();  in visitBitTestHeader()
2018   B.Reg = FuncInfo.CreateReg(B.RegVT);  in visitBitTestHeader()
2047   MVT VT = BB.RegVT;  in visitBitTestCase()
6029       MVT RegVT = *PhysReg.second->vt_begin();  in GetRegistersForValue()  local
6030       if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {  in GetRegistersForValue()
6032                                          RegVT, OpInfo.CallOperand);  in GetRegistersForValue()
6033         OpInfo.ConstraintVT = RegVT;  in GetRegistersForValue()
6034       } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {  in GetRegistersForValue()
6039         RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());  in GetRegistersForValue()
6041                                          RegVT, OpInfo.CallOperand);  in GetRegistersForValue()
6042         OpInfo.ConstraintVT = RegVT;  in GetRegistersForValue()
6049   MVT RegVT;  in GetRegistersForValue()  local
6062     RegVT = *RC->vt_begin();  in GetRegistersForValue()
6081     OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);  in GetRegistersForValue()
6088     RegVT = *RC->vt_begin();  in GetRegistersForValue()
6090       ValueVT = RegVT;  in GetRegistersForValue()
6097     OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT);  in GetRegistersForValue()
6445           MVT RegVT = AsmNodeOperands[CurOp+1].getSimpleValueType();  in visitInlineAsm()  local
6446           MatchedRegs.RegVTs.push_back(RegVT);  in visitInlineAsm()
6450             if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT))  in visitInlineAsm()
7438     MVT RegVT = TLI->getRegisterType(*CurDAG->getContext(), VT);  in LowerArguments()  local
7441                                         RegVT, VT, nullptr, AssertOp);  in LowerArguments()
7445     unsigned SRetReg = RegInfo.createVirtualRegister(TLI->getRegClassFor(RegVT));  in LowerArguments()