Lines Matching refs:MI
65 MachineBasicBlock::iterator MI) const { in insertNoop()
121 MachineInstr *TargetInstrInfo::commuteInstructionImpl(MachineInstr *MI, in commuteInstructionImpl() argument
125 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstructionImpl()
127 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstructionImpl()
133 assert(findCommutedOpIndices(MI, CommutableOpIdx1, CommutableOpIdx2) && in commuteInstructionImpl()
136 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstructionImpl()
139 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstructionImpl()
140 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstructionImpl()
141 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstructionImpl()
142 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstructionImpl()
143 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg(); in commuteInstructionImpl()
144 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg(); in commuteInstructionImpl()
145 bool Reg1IsKill = MI->getOperand(Idx1).isKill(); in commuteInstructionImpl()
146 bool Reg2IsKill = MI->getOperand(Idx2).isKill(); in commuteInstructionImpl()
147 bool Reg1IsUndef = MI->getOperand(Idx1).isUndef(); in commuteInstructionImpl()
148 bool Reg2IsUndef = MI->getOperand(Idx2).isUndef(); in commuteInstructionImpl()
149 bool Reg1IsInternal = MI->getOperand(Idx1).isInternalRead(); in commuteInstructionImpl()
150 bool Reg2IsInternal = MI->getOperand(Idx2).isInternalRead(); in commuteInstructionImpl()
154 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
159 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
167 MachineFunction &MF = *MI->getParent()->getParent(); in commuteInstructionImpl()
168 MI = MF.CloneMachineInstr(MI); in commuteInstructionImpl()
172 MI->getOperand(0).setReg(Reg0); in commuteInstructionImpl()
173 MI->getOperand(0).setSubReg(SubReg0); in commuteInstructionImpl()
175 MI->getOperand(Idx2).setReg(Reg1); in commuteInstructionImpl()
176 MI->getOperand(Idx1).setReg(Reg2); in commuteInstructionImpl()
177 MI->getOperand(Idx2).setSubReg(SubReg1); in commuteInstructionImpl()
178 MI->getOperand(Idx1).setSubReg(SubReg2); in commuteInstructionImpl()
179 MI->getOperand(Idx2).setIsKill(Reg1IsKill); in commuteInstructionImpl()
180 MI->getOperand(Idx1).setIsKill(Reg2IsKill); in commuteInstructionImpl()
181 MI->getOperand(Idx2).setIsUndef(Reg1IsUndef); in commuteInstructionImpl()
182 MI->getOperand(Idx1).setIsUndef(Reg2IsUndef); in commuteInstructionImpl()
183 MI->getOperand(Idx2).setIsInternalRead(Reg1IsInternal); in commuteInstructionImpl()
184 MI->getOperand(Idx1).setIsInternalRead(Reg2IsInternal); in commuteInstructionImpl()
185 return MI; in commuteInstructionImpl()
188 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI, in commuteInstruction() argument
196 !findCommutedOpIndices(MI, OpIdx1, OpIdx2)) { in commuteInstruction()
197 assert(MI->isCommutable() && in commuteInstruction()
201 return commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2); in commuteInstruction()
235 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI, in findCommutedOpIndices() argument
238 assert(!MI->isBundle() && in findCommutedOpIndices()
241 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices()
253 if (!MI->getOperand(SrcOpIdx1).isReg() || in findCommutedOpIndices()
254 !MI->getOperand(SrcOpIdx2).isReg()) in findCommutedOpIndices()
261 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { in isUnpredicatedTerminator()
262 if (!MI->isTerminator()) return false; in isUnpredicatedTerminator()
265 if (MI->isBranch() && !MI->isBarrier()) in isUnpredicatedTerminator()
267 if (!MI->isPredicable()) in isUnpredicatedTerminator()
269 return !isPredicated(MI); in isUnpredicatedTerminator()
273 MachineInstr *MI, ArrayRef<MachineOperand> Pred) const { in PredicateInstruction() argument
276 assert(!MI->isBundle() && in PredicateInstruction()
279 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction()
280 if (!MI->isPredicable()) in PredicateInstruction()
283 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { in PredicateInstruction()
285 MachineOperand &MO = MI->getOperand(i); in PredicateInstruction()
302 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, in hasLoadFromStackSlot() argument
305 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), in hasLoadFromStackSlot()
306 oe = MI->memoperands_end(); in hasLoadFromStackSlot()
322 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI, in hasStoreToStackSlot() argument
325 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), in hasStoreToStackSlot()
326 oe = MI->memoperands_end(); in hasStoreToStackSlot()
379 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); in reMaterialize() local
380 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
381 MBB.insert(I, MI); in reMaterialize()
400 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI, in canFoldCopy() argument
402 assert(MI->isCopy() && "MI must be a COPY instruction"); in canFoldCopy()
403 if (MI->getNumOperands() != 2) in canFoldCopy()
407 const MachineOperand &FoldOp = MI->getOperand(FoldIdx); in canFoldCopy()
408 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx); in canFoldCopy()
419 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); in canFoldCopy()
436 static MachineInstr *foldPatchpoint(MachineFunction &MF, MachineInstr *MI, in foldPatchpoint() argument
440 switch (MI->getOpcode()) { in foldPatchpoint()
446 PatchPointOpers opers(MI); in foldPatchpoint()
462 MF.CreateMachineInstr(TII.get(MI->getOpcode()), MI->getDebugLoc(), true); in foldPatchpoint()
467 MIB.addOperand(MI->getOperand(i)); in foldPatchpoint()
469 for (unsigned i = StartIdx; i < MI->getNumOperands(); ++i) { in foldPatchpoint()
470 MachineOperand &MO = MI->getOperand(i); in foldPatchpoint()
498 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, in foldMemoryOperand() argument
503 if (MI->getOperand(Ops[i]).isDef()) in foldMemoryOperand()
508 MachineBasicBlock *MBB = MI->getParent(); in foldMemoryOperand()
514 if (MI->getOpcode() == TargetOpcode::STACKMAP || in foldMemoryOperand()
515 MI->getOpcode() == TargetOpcode::PATCHPOINT) { in foldMemoryOperand()
517 NewMI = foldPatchpoint(MF, MI, Ops, FI, *this); in foldMemoryOperand()
519 MBB->insert(MI, NewMI); in foldMemoryOperand()
522 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, FI); in foldMemoryOperand()
526 NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in foldMemoryOperand()
545 if (!MI->isCopy() || Ops.size() != 1) in foldMemoryOperand()
548 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]); in foldMemoryOperand()
552 const MachineOperand &MO = MI->getOperand(1-Ops[0]); in foldMemoryOperand()
553 MachineBasicBlock::iterator Pos = MI; in foldMemoryOperand()
777 MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, in foldMemoryOperand() argument
783 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); in foldMemoryOperand()
785 MachineBasicBlock &MBB = *MI->getParent(); in foldMemoryOperand()
792 if ((MI->getOpcode() == TargetOpcode::STACKMAP || in foldMemoryOperand()
793 MI->getOpcode() == TargetOpcode::PATCHPOINT) && in foldMemoryOperand()
796 NewMI = foldPatchpoint(MF, MI, Ops, FrameIndex, *this); in foldMemoryOperand()
798 NewMI = MBB.insert(MI, NewMI); in foldMemoryOperand()
801 NewMI = foldMemoryOperandImpl(MF, MI, Ops, MI, LoadMI); in foldMemoryOperand()
807 if (MI->memoperands_empty()) { in foldMemoryOperand()
813 NewMI->setMemRefs(MI->memoperands_begin(), in foldMemoryOperand()
814 MI->memoperands_end()); in foldMemoryOperand()
824 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI, in isReallyTriviallyReMaterializableGeneric() argument
826 const MachineFunction &MF = *MI->getParent()->getParent(); in isReallyTriviallyReMaterializableGeneric()
830 if (!MI->getNumOperands() || !MI->getOperand(0).isReg()) in isReallyTriviallyReMaterializableGeneric()
832 unsigned DefReg = MI->getOperand(0).getReg(); in isReallyTriviallyReMaterializableGeneric()
839 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg)) in isReallyTriviallyReMaterializableGeneric()
846 if (isLoadFromStackSlot(MI, FrameIdx) && in isReallyTriviallyReMaterializableGeneric()
851 if (MI->isNotDuplicable() || MI->mayStore() || in isReallyTriviallyReMaterializableGeneric()
852 MI->hasUnmodeledSideEffects()) in isReallyTriviallyReMaterializableGeneric()
857 if (MI->isInlineAsm()) in isReallyTriviallyReMaterializableGeneric()
861 if (MI->mayLoad() && !MI->isInvariantLoad(AA)) in isReallyTriviallyReMaterializableGeneric()
866 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in isReallyTriviallyReMaterializableGeneric()
867 const MachineOperand &MO = MI->getOperand(i); in isReallyTriviallyReMaterializableGeneric()
904 int TargetInstrInfo::getSPAdjust(const MachineInstr *MI) const { in getSPAdjust()
905 const MachineFunction *MF = MI->getParent()->getParent(); in getSPAdjust()
913 if (MI->getOpcode() != FrameSetupOpcode && in getSPAdjust()
914 MI->getOpcode() != FrameDestroyOpcode) in getSPAdjust()
917 int SPAdj = MI->getOperand(0).getImm(); in getSPAdjust()
920 if ((!StackGrowsDown && MI->getOpcode() == FrameSetupOpcode) || in getSPAdjust()
921 (StackGrowsDown && MI->getOpcode() == FrameDestroyOpcode)) in getSPAdjust()
930 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI, in isSchedulingBoundary() argument
934 if (MI->isTerminator() || MI->isPosition()) in isSchedulingBoundary()
944 return MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI); in isSchedulingBoundary()
1015 const MachineInstr *MI) const { in getNumMicroOps()
1019 unsigned Class = MI->getDesc().getSchedClass(); in getNumMicroOps()
1047 const MachineInstr *MI, in getInstrLatency() argument
1052 return MI->mayLoad() ? 2 : 1; in getInstrLatency()
1054 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrLatency()
1139 const MachineInstr &MI, unsigned DefIdx, in getRegSequenceInputs() argument
1141 assert((MI.isRegSequence() || in getRegSequenceInputs()
1142 MI.isRegSequenceLike()) && "Instruction do not have the proper type"); in getRegSequenceInputs()
1144 if (!MI.isRegSequence()) in getRegSequenceInputs()
1145 return getRegSequenceLikeInputs(MI, DefIdx, InputRegs); in getRegSequenceInputs()
1150 for (unsigned OpIdx = 1, EndOpIdx = MI.getNumOperands(); OpIdx != EndOpIdx; in getRegSequenceInputs()
1152 const MachineOperand &MOReg = MI.getOperand(OpIdx); in getRegSequenceInputs()
1153 const MachineOperand &MOSubIdx = MI.getOperand(OpIdx + 1); in getRegSequenceInputs()
1164 const MachineInstr &MI, unsigned DefIdx, in getExtractSubregInputs() argument
1166 assert((MI.isExtractSubreg() || in getExtractSubregInputs()
1167 MI.isExtractSubregLike()) && "Instruction do not have the proper type"); in getExtractSubregInputs()
1169 if (!MI.isExtractSubreg()) in getExtractSubregInputs()
1170 return getExtractSubregLikeInputs(MI, DefIdx, InputReg); in getExtractSubregInputs()
1175 const MachineOperand &MOReg = MI.getOperand(1); in getExtractSubregInputs()
1176 const MachineOperand &MOSubIdx = MI.getOperand(2); in getExtractSubregInputs()
1187 const MachineInstr &MI, unsigned DefIdx, in getInsertSubregInputs() argument
1189 assert((MI.isInsertSubreg() || in getInsertSubregInputs()
1190 MI.isInsertSubregLike()) && "Instruction do not have the proper type"); in getInsertSubregInputs()
1192 if (!MI.isInsertSubreg()) in getInsertSubregInputs()
1193 return getInsertSubregLikeInputs(MI, DefIdx, BaseReg, InsertedReg); in getInsertSubregInputs()
1198 const MachineOperand &MOBaseReg = MI.getOperand(1); in getInsertSubregInputs()
1199 const MachineOperand &MOInsertedReg = MI.getOperand(2); in getInsertSubregInputs()
1200 const MachineOperand &MOSubIdx = MI.getOperand(3); in getInsertSubregInputs()