Lines Matching refs:KillMI
221 MachineInstr *KillMI = nullptr; in sink3AddrInstruction() local
233 KillMI = LIS->getInstructionFromIndex(I->end); in sink3AddrInstruction()
235 if (!KillMI) { in sink3AddrInstruction()
239 KillMI = UseMO.getParent(); in sink3AddrInstruction()
247 if (!KillMI || KillMI->getParent() != MBB || KillMI == MI || in sink3AddrInstruction()
248 KillMI == OldPos || KillMI->isTerminator()) in sink3AddrInstruction()
258 MachineBasicBlock::iterator KillPos = KillMI; in sink3AddrInstruction()
281 if (OtherMI == KillMI && MOReg == SavedReg) in sink3AddrInstruction()
300 LV->replaceKillInstruction(SavedReg, KillMI, MI); in sink3AddrInstruction()
832 MachineInstr *KillMI = nullptr; in rescheduleMIBelowKill() local
844 KillMI = LIS->getInstructionFromIndex(I->end); in rescheduleMIBelowKill()
846 KillMI = LV->getVarInfo(Reg).findKill(MBB); in rescheduleMIBelowKill()
848 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) in rescheduleMIBelowKill()
852 if (KillMI->hasUnmodeledSideEffects() || KillMI->isCall() || in rescheduleMIBelowKill()
853 KillMI->isBranch() || KillMI->isTerminator()) in rescheduleMIBelowKill()
858 if (isTwoAddrUse(*KillMI, Reg, DstReg)) in rescheduleMIBelowKill()
900 MachineBasicBlock::iterator KillPos = KillMI; in rescheduleMIBelowKill()
942 assert((MOReg != Reg || OtherMI == KillMI) && in rescheduleMIBelowKill()
975 LV->removeVirtualRegisterKilled(Reg, KillMI); in rescheduleMIBelowKill()
979 DEBUG(dbgs() << "\trescheduled below kill: " << *KillMI); in rescheduleMIBelowKill()
1021 MachineInstr *KillMI = nullptr; in rescheduleKillAboveMI() local
1033 KillMI = LIS->getInstructionFromIndex(I->end); in rescheduleKillAboveMI()
1035 KillMI = LV->getVarInfo(Reg).findKill(MBB); in rescheduleKillAboveMI()
1037 if (!KillMI || MI == KillMI || KillMI->isCopy() || KillMI->isCopyLike()) in rescheduleKillAboveMI()
1042 if (isTwoAddrUse(*KillMI, Reg, DstReg)) in rescheduleKillAboveMI()
1046 if (!KillMI->isSafeToMove(AA, SeenStore)) in rescheduleKillAboveMI()
1053 for (const MachineOperand &MO : KillMI->operands()) { in rescheduleKillAboveMI()
1062 bool isKill = MO.isKill() || (LIS && isPlainlyKilled(KillMI, MOReg, LIS)); in rescheduleKillAboveMI()
1077 MachineBasicBlock::iterator KillPos = KillMI; in rescheduleKillAboveMI()
1130 MachineBasicBlock::iterator From = KillMI; in rescheduleKillAboveMI()
1141 LIS->handleMove(KillMI); in rescheduleKillAboveMI()
1143 LV->removeVirtualRegisterKilled(Reg, KillMI); in rescheduleKillAboveMI()
1147 DEBUG(dbgs() << "\trescheduled kill: " << *KillMI); in rescheduleKillAboveMI()