158   MachineInstr *CmpMI;  member in __anon2dd089570111::SSACCmpConv
188   bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
381                                      const MachineInstr *CmpMI) {  in canSpeculateInstrs()  argument
425     if (&I != CmpMI && I.modifiesRegister(AArch64::NZCV, TRI)) {  in canSpeculateInstrs()
552   CmpMI = findConvertibleCompare(CmpBB);  in canConvert()
553   if (!CmpMI)  in canConvert()
556   if (!canSpeculateInstrs(CmpBB, CmpMI)) {  in canConvert()
615   switch (CmpMI->getOpcode()) {  in convert()
651   MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),  in convert()
653   if (CmpMI->getOperand(FirstOp + 1).isReg())  in convert()
654     MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),  in convert()
657       BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)  in convert()
658           .addOperand(CmpMI->getOperand(FirstOp)); // Register Rn  in convert()
662     MIB.addOperand(CmpMI->getOperand(FirstOp + 1)); // Register Rm / Immediate  in convert()
668     bool isNZ = CmpMI->getOpcode() == AArch64::CBNZW ||  in convert()
669                 CmpMI->getOpcode() == AArch64::CBNZX;  in convert()
670     BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), TII->get(AArch64::Bcc))  in convert()
672         .addOperand(CmpMI->getOperand(1)); // Branch target.  in convert()
674   CmpMI->eraseFromParent();  in convert()
705   switch (CmpMI->getOpcode()) {  in expectedCodeSizeDelta()