189   unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
190   unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
2720   MVT DestVT;  in selectFPToInt()  local
2721   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectFPToInt()
2735       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr;  in selectFPToInt()
2737       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr;  in selectFPToInt()
2740       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr;  in selectFPToInt()
2742       Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr;  in selectFPToInt()
2745       DestVT == MVT::i32 ? &AArch64::GPR32RegClass : &AArch64::GPR64RegClass);  in selectFPToInt()
2753   MVT DestVT;  in selectIntToFP()  local
2754   if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())  in selectIntToFP()
2756   assert ((DestVT == MVT::f32 || DestVT == MVT::f64) &&  in selectIntToFP()
2778       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri;  in selectIntToFP()
2780       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri;  in selectIntToFP()
2783       Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri;  in selectIntToFP()
2785       Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri;  in selectIntToFP()
2788   unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,  in selectIntToFP()
2933       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
2935       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);  in processCallArgs()
2943       MVT DestVT = VA.getLocVT();  in processCallArgs()  local
2945       ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);  in processCallArgs()
3706     MVT DestVT = VA.getValVT();  in selectRet()  local
3708     if (RVVT != DestVT) {  in selectRet()
3716       SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);  in selectRet()
3749   MVT DestVT = DestEVT.getSimpleVT();  in selectTrunc()  local
3754   if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8 &&  in selectTrunc()
3755       DestVT != MVT::i1)  in selectTrunc()
3771     switch (DestVT.SimpleTy) {  in selectTrunc()
3802 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {  in emiti1Ext()  argument
3803   assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||  in emiti1Ext()
3804           DestVT == MVT::i64) &&  in emiti1Ext()
3807   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emiti1Ext()
3808     DestVT = MVT::i32;  in emiti1Ext()
3813     if (DestVT == MVT::i64) {  in emiti1Ext()
3826     if (DestVT == MVT::i64) {  in emiti1Ext()
4211 unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,  in emitIntExt()  argument
4213   assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");  in emitIntExt()
4219   if (((DestVT != MVT::i8) && (DestVT != MVT::i16) &&  in emitIntExt()
4220        (DestVT != MVT::i32) && (DestVT != MVT::i64)) ||  in emitIntExt()
4232     return emiti1Ext(SrcReg, DestVT, IsZExt);  in emitIntExt()
4234     if (DestVT == MVT::i64)  in emitIntExt()
4241     if (DestVT == MVT::i64)  in emitIntExt()
4248     assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");  in emitIntExt()
4255   if (DestVT == MVT::i8 || DestVT == MVT::i16)  in emitIntExt()
4256     DestVT = MVT::i32;  in emitIntExt()
4257   else if (DestVT == MVT::i64) {  in emitIntExt()
4268       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in emitIntExt()
4432   MVT DestVT = DestEVT.getSimpleVT();  in selectRem()  local
4433   if (DestVT != MVT::i64 && DestVT != MVT::i32)  in selectRem()
4437   bool Is64bit = (DestVT == MVT::i64);  in selectRem()
4460       (DestVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;  in selectRem()