204   unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
206   unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
208   unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
1528 unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp()  argument
1553     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);  in emitLogicalOp()
1575       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1591         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1604   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in emitLogicalOp()
1612 unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_ri()  argument
1632     unsigned Idx = ISDOpc - ISD::AND;  in emitLogicalOp_ri()
1639     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_ri()
1651   if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {  in emitLogicalOp_ri()
1658 unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,  in emitLogicalOp_rs()  argument
1683     Opc = OpcTable[ISDOpc - ISD::AND][0];  in emitLogicalOp_rs()
1687     Opc = OpcTable[ISDOpc - ISD::AND][1];  in emitLogicalOp_rs()