Lines Matching refs:IsZExt
161 bool WantResult = true, bool IsZExt = false);
181 bool emitCmp(const Value *LHS, const Value *RHS, bool IsZExt);
182 bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
193 bool IsZExt = false);
197 bool IsZExt = false);
221 uint64_t Imm, bool IsZExt = true);
225 uint64_t Imm, bool IsZExt = true);
229 uint64_t Imm, bool IsZExt = false);
271 bool IsZExt = isa<ZExtInst>(I); in isIntExtFree() local
278 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) in isIntExtFree()
1091 bool WantResult, bool IsZExt) { in emitAddSub() argument
1102 ExtendType = IsZExt ? AArch64_AM::UXTB : AArch64_AM::SXTB; in emitAddSub()
1106 ExtendType = IsZExt ? AArch64_AM::UXTH : AArch64_AM::SXTH; in emitAddSub()
1139 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1143 uint64_t Imm = IsZExt ? C->getZExtValue() : C->getSExtValue(); in emitAddSub()
1237 RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt); in emitAddSub()
1406 bool AArch64FastISel::emitCmp(const Value *LHS, const Value *RHS, bool IsZExt) { in emitCmp() argument
1421 return emitICmp(VT, LHS, RHS, IsZExt); in emitCmp()
1429 bool IsZExt) { in emitICmp() argument
1431 IsZExt) != 0; in emitICmp()
1476 bool SetFlags, bool WantResult, bool IsZExt) { in emitAdd() argument
1478 IsZExt); in emitAdd()
1506 bool SetFlags, bool WantResult, bool IsZExt) { in emitSub() argument
1508 IsZExt); in emitSub()
3715 bool IsZExt = Outs[0].Flags.isZExt(); in selectRet() local
3716 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt); in selectRet()
3802 unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) { in emiti1Ext() argument
3810 if (IsZExt) { in emiti1Ext()
3903 bool IsZExt) { in emitLSL_ri() argument
3928 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSL_ri()
3967 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSL_ri()
4010 bool IsZExt) { in emitLSR_ri() argument
4035 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4067 if (Shift >= SrcBits && IsZExt) in emitLSR_ri()
4072 if (!IsZExt) { in emitLSR_ri()
4073 Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitLSR_ri()
4079 IsZExt = true; in emitLSR_ri()
4088 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSR_ri()
4131 bool IsZExt) { in emitASR_ri() argument
4156 return emitIntExt(SrcVT, Op0, RetVT, IsZExt); in emitASR_ri()
4188 if (Shift >= SrcBits && IsZExt) in emitASR_ri()
4197 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitASR_ri()
4212 bool IsZExt) { in emitIntExt() argument
4232 return emiti1Ext(SrcReg, DestVT, IsZExt); in emitIntExt()
4235 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4237 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4242 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4244 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4249 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4337 bool IsZExt = isa<ZExtInst>(I); in optimizeIntExtLoad() local
4345 if (!(IsZExt && isZExtLoad(LoadMI)) && !(!IsZExt && isSExtLoad(LoadMI))) in optimizeIntExtLoad()
4354 if (IsZExt) { in optimizeIntExtLoad()
4394 bool IsZExt = isa<ZExtInst>(I); in selectIntExt() local
4396 if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) { in selectIntExt()
4419 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); in selectIntExt()
4492 bool IsZExt = true; in selectMul() local
4498 IsZExt = true; in selectMul()
4507 IsZExt = false; in selectMul()
4519 emitLSL_ri(VT, SrcVT, Src0Reg, Src0IsKill, ShiftVal, IsZExt); in selectMul()
4558 bool IsZExt = I->getOpcode() != Instruction::AShr; in selectShift() local
4565 IsZExt = true; in selectShift()
4574 IsZExt = false; in selectShift()
4588 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4591 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()
4594 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt); in selectShift()