Lines Matching refs:LHSReg
162 unsigned emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg,
165 unsigned emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg,
168 unsigned emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg,
173 unsigned emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg,
183 bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
198 unsigned emitSubs_rr(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
200 unsigned emitSubs_rs(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
206 unsigned emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
208 unsigned emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT, unsigned LHSReg,
211 unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
1133 unsigned LHSReg = getRegForValue(LHS); in emitAddSub() local
1134 if (!LHSReg) in emitAddSub()
1139 LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt); in emitAddSub()
1145 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm, in emitAddSub()
1148 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags, in emitAddSub()
1152 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags, in emitAddSub()
1168 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1176 return emitAddSub_rx(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1196 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1221 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, in emitAddSub()
1239 return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitAddSub()
1243 unsigned AArch64FastISel::emitAddSub_rr(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rr() argument
1247 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rr()
1269 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1272 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rr()
1277 unsigned AArch64FastISel::emitAddSub_ri(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_ri() argument
1280 assert(LHSReg && "Invalid register number."); in emitAddSub_ri()
1314 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1316 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_ri()
1322 unsigned AArch64FastISel::emitAddSub_rs(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rs() argument
1328 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rs()
1354 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1357 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rs()
1363 unsigned AArch64FastISel::emitAddSub_rx(bool UseAdd, MVT RetVT, unsigned LHSReg, in emitAddSub_rx() argument
1369 assert(LHSReg && RHSReg && "Invalid register number."); in emitAddSub_rx()
1397 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1400 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rx()
1434 bool AArch64FastISel::emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitICmp_ri() argument
1436 return emitAddSub_ri(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, Imm, in emitICmp_ri()
1451 unsigned LHSReg = getRegForValue(LHS); in emitFCmp() local
1452 if (!LHSReg) in emitFCmp()
1459 .addReg(LHSReg, getKillRegState(LHSIsKill)); in emitFCmp()
1470 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitFCmp()
1511 unsigned AArch64FastISel::emitSubs_rr(MVT RetVT, unsigned LHSReg, in emitSubs_rr() argument
1514 return emitAddSub_rr(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rr()
1518 unsigned AArch64FastISel::emitSubs_rs(MVT RetVT, unsigned LHSReg, in emitSubs_rs() argument
1523 return emitAddSub_rs(/*UseAdd=*/false, RetVT, LHSReg, LHSIsKill, RHSReg, in emitSubs_rs()
1545 unsigned LHSReg = getRegForValue(LHS); in emitLogicalOp() local
1546 if (!LHSReg) in emitLogicalOp()
1553 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm); in emitLogicalOp()
1575 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1591 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg, in emitLogicalOp()
1604 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in emitLogicalOp()
1613 unsigned LHSReg, bool LHSIsKill, in emitLogicalOp_ri() argument
1649 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill, in emitLogicalOp_ri()
1659 unsigned LHSReg, bool LHSIsKill, in emitLogicalOp_rs() argument
1692 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitLogicalOp_rs()
1701 unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, in emitAnd_ri() argument
1703 return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm); in emitAnd_ri()
3553 unsigned LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
3554 if (!LHSReg) in fastLowerIntrinsicCall()
3564 MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
3577 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, in fastLowerIntrinsicCall()
3579 unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()
3588 unsigned LHSReg = getRegForValue(LHS); in fastLowerIntrinsicCall() local
3589 if (!LHSReg) in fastLowerIntrinsicCall()
3599 MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill); in fastLowerIntrinsicCall()
3609 MulReg = emitMul_rr(VT, LHSReg, /*IsKill=*/false, RHSReg, in fastLowerIntrinsicCall()
3611 unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill, in fastLowerIntrinsicCall()