194   unsigned emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill, int64_t Imm);
212   unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
214   unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
216   unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
218   unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
220   unsigned emitLSL_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
222   unsigned emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
224   unsigned emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
226   unsigned emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
228   unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
1486 unsigned AArch64FastISel::emitAdd_ri_(MVT VT, unsigned Op0, bool Op0IsKill,  in emitAdd_ri_()  argument
1490     ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);  in emitAdd_ri_()
1492     ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);  in emitAdd_ri_()
1501   ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);  in emitAdd_ri_()
3476     bool Op0IsKill = hasTrivialKill(II->getOperand(0));  in fastLowerIntrinsicCall()  local
3478     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);  in fastLowerIntrinsicCall()
3835 unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitMul_rr()  argument
3851   return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill,  in emitMul_rr()
3855 unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitSMULL_rr()  argument
3861                           Op0, Op0IsKill, Op1, Op1IsKill,  in emitSMULL_rr()
3865 unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,  in emitUMULL_rr()  argument
3871                           Op0, Op0IsKill, Op1, Op1IsKill,  in emitUMULL_rr()
3875 unsigned AArch64FastISel::emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSL_rr()  argument
3894   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSL_rr()
3902                                      bool Op0IsKill, uint64_t Shift,  in emitLSL_ri()  argument
3925           .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSL_ri()
3973         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSL_ri()
3976     Op0IsKill = true;  in emitLSL_ri()
3978   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitLSL_ri()
3981 unsigned AArch64FastISel::emitLSR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitLSR_rr()  argument
3997     Op0Reg = emitAnd_ri(MVT::i32, Op0Reg, Op0IsKill, Mask);  in emitLSR_rr()
3999     Op0IsKill = Op1IsKill = true;  in emitLSR_rr()
4001   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSR_rr()
4009                                      bool Op0IsKill, uint64_t Shift,  in emitLSR_ri()  argument
4032       .addReg(Op0, getKillRegState(Op0IsKill));  in emitLSR_ri()
4076     Op0IsKill = true;  in emitLSR_ri()
4094         .addReg(Op0, getKillRegState(Op0IsKill))  in emitLSR_ri()
4097     Op0IsKill = true;  in emitLSR_ri()
4099   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitLSR_ri()
4102 unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,  in emitASR_rr()  argument
4120     Op0IsKill = Op1IsKill = true;  in emitASR_rr()
4122   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitASR_rr()
4130                                      bool Op0IsKill, uint64_t Shift,  in emitASR_ri()  argument
4153       .addReg(Op0, getKillRegState(Op0IsKill));  in emitASR_ri()
4203         .addReg(Op0, getKillRegState(Op0IsKill))  in emitASR_ri()
4206     Op0IsKill = true;  in emitASR_ri()
4208   return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);  in emitASR_ri()
4583     bool Op0IsKill = hasTrivialKill(Op0);  in selectShift()  local
4588       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4591       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4594       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4607   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectShift()  local
4618     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4621     ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4624     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4666   bool Op0IsKill = hasTrivialKill(I->getOperand(0));  in selectBitCast()  local
4667   unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);  in selectBitCast()