Lines Matching refs:Opc
370 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi; in materializeFP() local
371 return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); in materializeFP()
403 unsigned Opc = Is64Bit ? AArch64::LDRDui : AArch64::LDRSui; in materializeFP() local
405 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in materializeFP()
491 unsigned Opc = Is64Bit ? AArch64::FMOVXDr : AArch64::FMOVWSr; in fastMaterializeFloatZero() local
492 return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); in fastMaterializeFloatZero()
1259 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rr() local
1268 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_rr()
1301 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_ri() local
1313 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_ri()
1344 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rs() local
1353 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_rs()
1384 unsigned Opc = OpcTable[SetFlags][UseAdd][Is64Bit]; in emitAddSub_rx() local
1396 const MCInstrDesc &II = TII.get(Opc); in emitAddSub_rx()
1457 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDri : AArch64::FCMPSri; in emitFCmp() local
1458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in emitFCmp()
1468 unsigned Opc = (RetVT == MVT::f64) ? AArch64::FCMPDrr : AArch64::FCMPSrr; in emitFCmp() local
1469 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in emitFCmp()
1623 unsigned Opc; in emitLogicalOp_ri() local
1633 Opc = OpcTable[Idx][0]; in emitLogicalOp_ri()
1639 Opc = OpcTable[ISDOpc - ISD::AND][1]; in emitLogicalOp_ri()
1649 fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill, in emitLogicalOp_ri()
1675 unsigned Opc; in emitLogicalOp_rs() local
1683 Opc = OpcTable[ISDOpc - ISD::AND][0]; in emitLogicalOp_rs()
1687 Opc = OpcTable[ISDOpc - ISD::AND][1]; in emitLogicalOp_rs()
1692 fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill, in emitLogicalOp_rs()
1773 unsigned Opc; in emitLoad() local
1788 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][0]; in emitLoad()
1793 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][1]; in emitLoad()
1798 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][2]; in emitLoad()
1803 Opc = GPOpcTable[WantZExt][2 * Idx + IsRet64Bit][3]; in emitLoad()
1807 Opc = FPOpcTable[Idx][0]; in emitLoad()
1811 Opc = FPOpcTable[Idx][1]; in emitLoad()
1819 TII.get(Opc), ResultReg); in emitLoad()
2025 unsigned Opc; in emitStore() local
2037 case MVT::i8: Opc = OpcTable[Idx][0]; break; in emitStore()
2038 case MVT::i16: Opc = OpcTable[Idx][1]; break; in emitStore()
2039 case MVT::i32: Opc = OpcTable[Idx][2]; break; in emitStore()
2040 case MVT::i64: Opc = OpcTable[Idx][3]; break; in emitStore()
2041 case MVT::f32: Opc = OpcTable[Idx][4]; break; in emitStore()
2042 case MVT::f64: Opc = OpcTable[Idx][5]; break; in emitStore()
2052 const MCInstrDesc &II = TII.get(Opc); in emitStore()
2239 unsigned Opc = OpcTable[IsBitTest][IsCmpNE][Is64Bit]; in emitCompareAndBranch() local
2240 const MCInstrDesc &II = TII.get(Opc); in emitCompareAndBranch()
2257 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)) in emitCompareAndBranch()
2506 unsigned Opc = 0; in optimizeSelect() local
2512 Opc = AArch64::ORRWrr; in optimizeSelect()
2517 Opc = AArch64::BICWrr; in optimizeSelect()
2523 Opc = AArch64::ORRWrr; in optimizeSelect()
2529 Opc = AArch64::ANDWrr; in optimizeSelect()
2533 if (!Opc) in optimizeSelect()
2550 unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, in optimizeSelect()
2562 unsigned Opc; in selectSelect() local
2571 Opc = AArch64::CSELWr; in selectSelect()
2575 Opc = AArch64::CSELXr; in selectSelect()
2579 Opc = AArch64::FCSELSrrr; in selectSelect()
2583 Opc = AArch64::FCSELDrrr; in selectSelect()
2676 Src2Reg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2680 unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg, in selectSelect()
2732 unsigned Opc; in selectFPToInt() local
2735 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWDr : AArch64::FCVTZSUXDr; in selectFPToInt()
2737 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWDr : AArch64::FCVTZUUXDr; in selectFPToInt()
2740 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZSUWSr : AArch64::FCVTZSUXSr; in selectFPToInt()
2742 Opc = (DestVT == MVT::i32) ? AArch64::FCVTZUUWSr : AArch64::FCVTZUUXSr; in selectFPToInt()
2746 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in selectFPToInt()
2775 unsigned Opc; in selectIntToFP() local
2778 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUXSri : AArch64::SCVTFUXDri; in selectIntToFP()
2780 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUXSri : AArch64::UCVTFUXDri; in selectIntToFP()
2783 Opc = (DestVT == MVT::f32) ? AArch64::SCVTFUWSri : AArch64::SCVTFUWDri; in selectIntToFP()
2785 Opc = (DestVT == MVT::f32) ? AArch64::UCVTFUWSri : AArch64::UCVTFUWDri; in selectIntToFP()
2788 unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg, in selectIntToFP()
3440 unsigned Opc; in fastLowerIntrinsicCall() local
3445 Opc = AArch64::FABSSr; in fastLowerIntrinsicCall()
3448 Opc = AArch64::FABSDr; in fastLowerIntrinsicCall()
3456 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastLowerIntrinsicCall()
3837 unsigned Opc, ZReg; in emitMul_rr() local
3844 Opc = AArch64::MADDWrrr; ZReg = AArch64::WZR; break; in emitMul_rr()
3846 Opc = AArch64::MADDXrrr; ZReg = AArch64::XZR; break; in emitMul_rr()
3851 return fastEmitInst_rrr(Opc, RC, Op0, Op0IsKill, Op1, Op1IsKill, in emitMul_rr()
3877 unsigned Opc = 0; in emitLSL_rr() local
3882 case MVT::i8: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSL_rr()
3883 case MVT::i16: Opc = AArch64::LSLVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSL_rr()
3884 case MVT::i32: Opc = AArch64::LSLVWr; break; in emitLSL_rr()
3885 case MVT::i64: Opc = AArch64::LSLVXr; break; in emitLSL_rr()
3894 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSL_rr()
3967 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSL_ri() local
3978 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitLSL_ri()
3983 unsigned Opc = 0; in emitLSR_rr() local
3988 case MVT::i8: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xff; break; in emitLSR_rr()
3989 case MVT::i16: Opc = AArch64::LSRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitLSR_rr()
3990 case MVT::i32: Opc = AArch64::LSRVWr; break; in emitLSR_rr()
3991 case MVT::i64: Opc = AArch64::LSRVXr; break; in emitLSR_rr()
4001 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitLSR_rr()
4088 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitLSR_ri() local
4099 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitLSR_ri()
4104 unsigned Opc = 0; in emitASR_rr() local
4109 case MVT::i8: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xff; break; in emitASR_rr()
4110 case MVT::i16: Opc = AArch64::ASRVWr; NeedTrunc = true; Mask = 0xffff; break; in emitASR_rr()
4111 case MVT::i32: Opc = AArch64::ASRVWr; break; in emitASR_rr()
4112 case MVT::i64: Opc = AArch64::ASRVXr; break; in emitASR_rr()
4122 unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg, in emitASR_rr()
4197 unsigned Opc = OpcTable[IsZExt][Is64Bit]; in emitASR_ri() local
4208 return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS); in emitASR_ri()
4225 unsigned Opc; in emitIntExt() local
4235 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4237 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4242 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4244 Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri; in emitIntExt()
4249 Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri; in emitIntExt()
4269 return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm); in emitIntExt()
4643 unsigned Opc; in selectBitCast() local
4645 Opc = AArch64::FMOVWSr; in selectBitCast()
4647 Opc = AArch64::FMOVXDr; in selectBitCast()
4649 Opc = AArch64::FMOVSWr; in selectBitCast()
4651 Opc = AArch64::FMOVDXr; in selectBitCast()
4667 unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill); in selectBitCast()