324     unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);  in fastMaterializeAlloca()  local
326             ResultReg)  in fastMaterializeAlloca()
330     return ResultReg;  in fastMaterializeAlloca()
347   unsigned ResultReg = createResultReg(RC);  in materializeInt()  local
349           ResultReg).addReg(ZeroReg, getKillRegState(true));  in materializeInt()
350   return ResultReg;  in materializeInt()
384     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));  in materializeFP()  local
386             TII.get(TargetOpcode::COPY), ResultReg)  in materializeFP()
389     return ResultReg;  in materializeFP()
404   unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));  in materializeFP()  local
405   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in materializeFP()
408   return ResultReg;  in materializeFP()
428   unsigned ResultReg;  in materializeGV()  local
436     ResultReg = createResultReg(&AArch64::GPR64RegClass);  in materializeGV()
438             ResultReg)  in materializeGV()
451     ResultReg = createResultReg(&AArch64::GPR64spRegClass);  in materializeGV()
453             ResultReg)  in materializeGV()
458   return ResultReg;  in materializeGV()
985     unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);  in simplifyAddress()  local
987             ResultReg)  in simplifyAddress()
992     Addr.setReg(ResultReg);  in simplifyAddress()
996     unsigned ResultReg = 0;  in simplifyAddress()  local
1000         ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),  in simplifyAddress()
1005         ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),  in simplifyAddress()
1011         ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),  in simplifyAddress()
1015         ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),  in simplifyAddress()
1019         ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),  in simplifyAddress()
1022     if (!ResultReg)  in simplifyAddress()
1025     Addr.setReg(ResultReg);  in simplifyAddress()
1034     unsigned ResultReg;  in simplifyAddress()  local
1037       ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), /*IsKill=*/false, Offset);  in simplifyAddress()
1039       ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);  in simplifyAddress()
1041     if (!ResultReg)  in simplifyAddress()
1043     Addr.setReg(ResultReg);  in simplifyAddress()
1141   unsigned ResultReg = 0;  in emitAddSub()  local
1145       ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, LHSIsKill, -Imm,  in emitAddSub()
1148       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, Imm, SetFlags,  in emitAddSub()
1152       ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, LHSIsKill, 0, SetFlags,  in emitAddSub()
1155   if (ResultReg)  in emitAddSub()
1156     return ResultReg;  in emitAddSub()
1196       ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1199       if (ResultReg)  in emitAddSub()
1200         return ResultReg;  in emitAddSub()
1221           ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitAddSub()
1224           if (ResultReg)  in emitAddSub()
1225             return ResultReg;  in emitAddSub()
1262   unsigned ResultReg;  in emitAddSub_rr()  local
1264     ResultReg = createResultReg(RC);  in emitAddSub_rr()
1266     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_rr()
1271   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_rr()
1274   return ResultReg;  in emitAddSub_rr()
1307   unsigned ResultReg;  in emitAddSub_ri()  local
1309     ResultReg = createResultReg(RC);  in emitAddSub_ri()
1311     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_ri()
1315   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_ri()
1319   return ResultReg;  in emitAddSub_ri()
1347   unsigned ResultReg;  in emitAddSub_rs()  local
1349     ResultReg = createResultReg(RC);  in emitAddSub_rs()
1351     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_rs()
1356   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_rs()
1360   return ResultReg;  in emitAddSub_rs()
1390   unsigned ResultReg;  in emitAddSub_rx()  local
1392     ResultReg = createResultReg(RC);  in emitAddSub_rx()
1394     ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;  in emitAddSub_rx()
1399   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)  in emitAddSub_rx()
1403   return ResultReg;  in emitAddSub_rx()
1488   unsigned ResultReg;  in emitAdd_ri_()  local
1490     ResultReg = emitAddSub_ri(false, VT, Op0, Op0IsKill, -Imm);  in emitAdd_ri_()
1492     ResultReg = emitAddSub_ri(true, VT, Op0, Op0IsKill, Imm);  in emitAdd_ri_()
1494   if (ResultReg)  in emitAdd_ri_()
1495     return ResultReg;  in emitAdd_ri_()
1501   ResultReg = emitAddSub_rr(true, VT, Op0, Op0IsKill, CReg, true);  in emitAdd_ri_()
1502   return ResultReg;  in emitAdd_ri_()
1550   unsigned ResultReg = 0;  in emitLogicalOp()  local
1553     ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, LHSIsKill, Imm);  in emitLogicalOp()
1555   if (ResultReg)  in emitLogicalOp()
1556     return ResultReg;  in emitLogicalOp()
1575       ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1577       if (ResultReg)  in emitLogicalOp()
1578         return ResultReg;  in emitLogicalOp()
1591         ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, LHSIsKill, RHSReg,  in emitLogicalOp()
1593         if (ResultReg)  in emitLogicalOp()
1594           return ResultReg;  in emitLogicalOp()
1604   ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);  in emitLogicalOp()
1607     ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);  in emitLogicalOp()
1609   return ResultReg;  in emitLogicalOp()
1648   unsigned ResultReg =  in emitLogicalOp_ri()  local
1653     ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);  in emitLogicalOp_ri()
1655   return ResultReg;  in emitLogicalOp_ri()
1691   unsigned ResultReg =  in emitLogicalOp_rs()  local
1696     ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);  in emitLogicalOp_rs()
1698   return ResultReg;  in emitLogicalOp_rs()
1817   unsigned ResultReg = createResultReg(RC);  in emitLoad()  local
1819                                     TII.get(Opc), ResultReg);  in emitLoad()
1824     unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, 1);  in emitLoad()
1826     ResultReg = ANDReg;  in emitLoad()
1836         .addReg(ResultReg, getKillRegState(true))  in emitLoad()
1838     ResultReg = Reg64;  in emitLoad()
1840   return ResultReg;  in emitLoad()
1851   unsigned ResultReg;  in selectAddSub()  local
1856     ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));  in selectAddSub()
1859     ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));  in selectAddSub()
1862   if (!ResultReg)  in selectAddSub()
1865   updateValueMap(I, ResultReg);  in selectAddSub()
1877   unsigned ResultReg;  in selectLogicalOp()  local
1882     ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
1885     ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
1888     ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));  in selectLogicalOp()
1891   if (!ResultReg)  in selectLogicalOp()
1894   updateValueMap(I, ResultReg);  in selectLogicalOp()
1931   unsigned ResultReg =  in selectLoad()  local
1933   if (!ResultReg)  in selectLoad()
1959           ResultReg = std::prev(FuncInfo.InsertPt)->getOperand(0).getReg();  in selectLoad()
1961           ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,  in selectLoad()
1965       updateValueMap(I, ResultReg);  in selectLoad()
1985     updateValueMap(IntExtVal, ResultReg);  in selectLoad()
1989   updateValueMap(I, ResultReg);  in selectLoad()
2424   unsigned ResultReg = 0;  in selectCmp()  local
2429     ResultReg = createResultReg(&AArch64::GPR32RegClass);  in selectCmp()
2431             TII.get(TargetOpcode::COPY), ResultReg)  in selectCmp()
2435     ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);  in selectCmp()
2439   if (ResultReg) {  in selectCmp()
2440     updateValueMap(I, ResultReg);  in selectCmp()
2448   ResultReg = createResultReg(&AArch64::GPR32RegClass);  in selectCmp()
2476             ResultReg)  in selectCmp()
2481     updateValueMap(I, ResultReg);  in selectCmp()
2490           ResultReg)  in selectCmp()
2495   updateValueMap(I, ResultReg);  in selectCmp()
2550   unsigned ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,  in optimizeSelect()  local
2552   updateValueMap(SI, ResultReg);  in optimizeSelect()
2680   unsigned ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src1IsKill, Src2Reg,  in selectSelect()  local
2682   updateValueMap(I, ResultReg);  in selectSelect()
2695   unsigned ResultReg = createResultReg(&AArch64::FPR64RegClass);  in selectFPExt()  local
2697           ResultReg).addReg(Op);  in selectFPExt()
2698   updateValueMap(I, ResultReg);  in selectFPExt()
2711   unsigned ResultReg = createResultReg(&AArch64::FPR32RegClass);  in selectFPTrunc()  local
2713           ResultReg).addReg(Op);  in selectFPTrunc()
2714   updateValueMap(I, ResultReg);  in selectFPTrunc()
2744   unsigned ResultReg = createResultReg(  in selectFPToInt()  local
2746   BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in selectFPToInt()
2748   updateValueMap(I, ResultReg);  in selectFPToInt()
2788   unsigned ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg,  in selectIntToFP()  local
2790   updateValueMap(I, ResultReg);  in selectIntToFP()
2894     unsigned ResultReg = createResultReg(RC);  in fastLowerArguments()  local
2896             TII.get(TargetOpcode::COPY), ResultReg)  in fastLowerArguments()
2898     updateValueMap(&Arg, ResultReg);  in fastLowerArguments()
3019     unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));  in finishCall()  local
3021             TII.get(TargetOpcode::COPY), ResultReg)  in finishCall()
3025     CLI.ResultReg = ResultReg;  in finishCall()
3191     unsigned ResultReg = emitLoad(VT, VT, Src);  in tryEmitSmallMemCpy()  local
3192     if (!ResultReg)  in tryEmitSmallMemCpy()
3195     if (!emitStore(VT, ResultReg, Dest))  in tryEmitSmallMemCpy()
3432     updateValueMap(II, CLI.ResultReg);  in fastLowerIntrinsicCall()
3455     unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));  in fastLowerIntrinsicCall()  local
3456     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)  in fastLowerIntrinsicCall()
3458     updateValueMap(II, ResultReg);  in fastLowerIntrinsicCall()
3478     unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);  in fastLowerIntrinsicCall()  local
3479     if (!ResultReg)  in fastLowerIntrinsicCall()
3482     updateValueMap(II, ResultReg);  in fastLowerIntrinsicCall()
3768   unsigned ResultReg;  in selectTrunc()  local
3789     ResultReg = emitAnd_ri(MVT::i32, Reg32, /*IsKill=*/true, Mask);  in selectTrunc()
3790     assert(ResultReg && "Unexpected AND instruction emission failure.");  in selectTrunc()
3792     ResultReg = createResultReg(&AArch64::GPR32RegClass);  in selectTrunc()
3794             TII.get(TargetOpcode::COPY), ResultReg)  in selectTrunc()
3798   updateValueMap(I, ResultReg);  in selectTrunc()
3811     unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);  in emiti1Ext()  local
3812     assert(ResultReg && "Unexpected AND instruction emission failure.");  in emiti1Ext()
3820           .addReg(ResultReg)  in emiti1Ext()
3822       ResultReg = Reg64;  in emiti1Ext()
3824     return ResultReg;  in emiti1Ext()
3894   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSL_rr()  local
3897     ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);  in emitLSL_rr()
3898   return ResultReg;  in emitLSL_rr()
3922       unsigned ResultReg = createResultReg(RC);  in emitLSL_ri()  local
3924               TII.get(TargetOpcode::COPY), ResultReg)  in emitLSL_ri()
3926       return ResultReg;  in emitLSL_ri()
4001   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitLSR_rr()  local
4004     ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);  in emitLSR_rr()
4005   return ResultReg;  in emitLSR_rr()
4029       unsigned ResultReg = createResultReg(RC);  in emitLSR_ri()  local
4031               TII.get(TargetOpcode::COPY), ResultReg)  in emitLSR_ri()
4033       return ResultReg;  in emitLSR_ri()
4122   unsigned ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op0IsKill, Op1Reg,  in emitASR_rr()  local
4125     ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);  in emitASR_rr()
4126   return ResultReg;  in emitASR_rr()
4150       unsigned ResultReg = createResultReg(RC);  in emitASR_ri()  local
4152               TII.get(TargetOpcode::COPY), ResultReg)  in emitASR_ri()
4154       return ResultReg;  in emitASR_ri()
4398         unsigned ResultReg = createResultReg(&AArch64::GPR64RegClass);  in selectIntExt()  local
4400                 TII.get(AArch64::SUBREG_TO_REG), ResultReg)  in selectIntExt()
4404         SrcReg = ResultReg;  in selectIntExt()
4419   unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);  in selectIntExt()  local
4420   if (!ResultReg)  in selectIntExt()
4423   updateValueMap(I, ResultReg);  in selectIntExt()
4466   unsigned ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, /*IsKill=*/true,  in selectRem()  local
4469   updateValueMap(I, ResultReg);  in selectRem()
4518       unsigned ResultReg =  in selectMul()  local
4521       if (ResultReg) {  in selectMul()
4522         updateValueMap(I, ResultReg);  in selectMul()
4537   unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);  in selectMul()  local
4539   if (!ResultReg)  in selectMul()
4542   updateValueMap(I, ResultReg);  in selectMul()
4555     unsigned ResultReg = 0;  in selectShift()  local
4588       ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4591       ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4594       ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, Op0IsKill, ShiftVal, IsZExt);  in selectShift()
4597     if (!ResultReg)  in selectShift()
4600     updateValueMap(I, ResultReg);  in selectShift()
4614   unsigned ResultReg = 0;  in selectShift()  local
4618     ResultReg = emitLSL_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4621     ResultReg = emitASR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4624     ResultReg = emitLSR_rr(RetVT, Op0Reg, Op0IsKill, Op1Reg, Op1IsKill);  in selectShift()
4628   if (!ResultReg)  in selectShift()
4631   updateValueMap(I, ResultReg);  in selectShift()
4667   unsigned ResultReg = fastEmitInst_r(Opc, RC, Op0Reg, Op0IsKill);  in selectBitCast()  local
4669   if (!ResultReg)  in selectBitCast()
4672   updateValueMap(I, ResultReg);  in selectBitCast()
4710   updateValueMap(I, CLI.ResultReg);  in selectFRem()
4734     unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Src0IsKill, Lg2);  in selectSDiv()  local
4735     if (!ResultReg)  in selectSDiv()
4737     updateValueMap(I, ResultReg);  in selectSDiv()
4768   unsigned ResultReg;  in selectSDiv()  local
4770     ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, /*IsKill=*/true,  in selectSDiv()
4773     ResultReg = emitASR_ri(VT, VT, SelectReg, /*IsKill=*/true, Lg2);  in selectSDiv()
4775   if (!ResultReg)  in selectSDiv()
4778   updateValueMap(I, ResultReg);  in selectSDiv()