Lines Matching refs:ShiftImm
171 uint64_t ShiftImm, bool SetFlags = false,
176 uint64_t ShiftImm, bool SetFlags = false,
202 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
210 uint64_t ShiftImm);
1285 unsigned ShiftImm; in emitAddSub_ri() local
1287 ShiftImm = 0; in emitAddSub_ri()
1289 ShiftImm = 12; in emitAddSub_ri()
1318 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1326 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1334 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1359 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
1367 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rx() argument
1374 if (ShiftImm >= 4) in emitAddSub_rx()
1402 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
1522 uint64_t ShiftImm, bool WantResult) { in emitSubs_rs() argument
1524 RHSIsKill, ShiftType, ShiftImm, /*SetFlags=*/true, in emitSubs_rs()
1661 uint64_t ShiftImm) { in emitLogicalOp_rs() argument
1671 if (ShiftImm >= RetVT.getSizeInBits()) in emitLogicalOp_rs()
1693 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitLogicalOp_rs()