Lines Matching refs:hasTrivialKill
703 bool RegIsKill = hasTrivialKill(LHS); in computeAddress()
801 bool RegIsKill = hasTrivialKill(LHS); in computeAddress()
1136 bool LHSIsKill = hasTrivialKill(LHS); in emitAddSub()
1167 bool RHSIsKill = hasTrivialKill(SI->getOperand(0)); in emitAddSub()
1175 bool RHSIsKill = hasTrivialKill(RHS); in emitAddSub()
1195 bool RHSIsKill = hasTrivialKill(MulLHS); in emitAddSub()
1220 bool RHSIsKill = hasTrivialKill(SI->getOperand(0)); in emitAddSub()
1234 bool RHSIsKill = hasTrivialKill(RHS); in emitAddSub()
1454 bool LHSIsKill = hasTrivialKill(LHS); in emitFCmp()
1466 bool RHSIsKill = hasTrivialKill(RHS); in emitFCmp()
1548 bool LHSIsKill = hasTrivialKill(LHS); in emitLogicalOp()
1574 bool RHSIsKill = hasTrivialKill(MulLHS); in emitLogicalOp()
1590 bool RHSIsKill = hasTrivialKill(SI->getOperand(0)); in emitLogicalOp()
1601 bool RHSIsKill = hasTrivialKill(RHS); in emitLogicalOp()
2245 bool SrcIsKill = hasTrivialKill(LHS); in emitCompareAndBranch()
2376 bool CondRegIsKill = hasTrivialKill(BI->getCondition()); in selectBranch()
2539 bool Src1IsKill = hasTrivialKill(Src1Val); in optimizeSelect()
2544 bool Src2IsKill = hasTrivialKill(Src2Val); in optimizeSelect()
2654 bool CondIsKill = hasTrivialKill(Cond); in selectSelect()
2667 bool Src1IsKill = hasTrivialKill(SI->getTrueValue()); in selectSelect()
2670 bool Src2IsKill = hasTrivialKill(SI->getFalseValue()); in selectSelect()
2762 bool SrcIsKill = hasTrivialKill(I->getOperand(0)); in selectIntToFP()
3454 bool SrcRegIsKill = hasTrivialKill(II->getOperand(0)); in fastLowerIntrinsicCall()
3476 bool Op0IsKill = hasTrivialKill(II->getOperand(0)); in fastLowerIntrinsicCall()
3556 bool LHSIsKill = hasTrivialKill(LHS); in fastLowerIntrinsicCall()
3561 bool RHSIsKill = hasTrivialKill(RHS); in fastLowerIntrinsicCall()
3591 bool LHSIsKill = hasTrivialKill(LHS); in fastLowerIntrinsicCall()
3596 bool RHSIsKill = hasTrivialKill(RHS); in fastLowerIntrinsicCall()
3761 bool SrcIsKill = hasTrivialKill(Op); in selectTrunc()
4391 bool SrcIsKill = hasTrivialKill(I->getOperand(0)); in selectIntExt()
4452 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectRem()
4457 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectRem()
4516 bool Src0IsKill = hasTrivialKill(Src0); in selectMul()
4530 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectMul()
4535 bool Src1IsKill = hasTrivialKill(I->getOperand(1)); in selectMul()
4583 bool Op0IsKill = hasTrivialKill(Op0); in selectShift()
4607 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); in selectShift()
4612 bool Op1IsKill = hasTrivialKill(I->getOperand(1)); in selectShift()
4666 bool Op0IsKill = hasTrivialKill(I->getOperand(0)); in selectBitCast()
4731 bool Src0IsKill = hasTrivialKill(I->getOperand(0)); in selectSDiv()
4791 bool IdxNIsKill = hasTrivialKill(Idx); in getRegForGEPIndex()
4812 bool NIsKill = hasTrivialKill(I->getOperand(0)); in selectGetElementPtr()