150   SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154   SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156   SDNode *SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158   SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159   SDNode *SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161   SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162   SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163   SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164   SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1018 SDNode *AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs,  in SelectTable()  argument
1028                                N->op_begin() + Vec0Off + NumVecs);  in SelectTable()
1035   Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));  in SelectTable()
1134 SDNode *AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs,  in SelectLoad()  argument
1147   for (unsigned i = 0; i < NumVecs; ++i)  in SelectLoad()
1151   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));  in SelectLoad()
1155 SDNode *AArch64DAGToDAGISel::SelectPostLoad(SDNode *N, unsigned NumVecs,  in SelectPostLoad()  argument
1171   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));  in SelectPostLoad()
1175   if (NumVecs == 1)  in SelectPostLoad()
1178     for (unsigned i = 0; i < NumVecs; ++i)  in SelectPostLoad()
1183   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));  in SelectPostLoad()
1187 SDNode *AArch64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,  in SelectStore()  argument
1194   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectStore()
1197   SDValue Ops[] = {RegSeq, N->getOperand(NumVecs + 2), N->getOperand(0)};  in SelectStore()
1203 SDNode *AArch64DAGToDAGISel::SelectPostStore(SDNode *N, unsigned NumVecs,  in SelectPostStore()  argument
1212   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostStore()
1216                    N->getOperand(NumVecs + 1), // base register  in SelectPostStore()
1217                    N->getOperand(NumVecs + 2), // Incremental  in SelectPostStore()
1259 SDNode *AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,  in SelectLoadLane()  argument
1266   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectLoadLane()
1277       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();  in SelectLoadLane()
1280                    N->getOperand(NumVecs + 3), N->getOperand(0)};  in SelectLoadLane()
1287   for (unsigned i = 0; i < NumVecs; ++i) {  in SelectLoadLane()
1294   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));  in SelectLoadLane()
1299 SDNode *AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,  in SelectPostLoadLane()  argument
1306   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostLoadLane()
1318       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();  in SelectPostLoadLane()
1323                    N->getOperand(NumVecs + 2),                  // Base register  in SelectPostLoadLane()
1324                    N->getOperand(NumVecs + 3),                  // Incremental  in SelectPostLoadLane()
1329   ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 0));  in SelectPostLoadLane()
1333   if (NumVecs == 1) {  in SelectPostLoadLane()
1340     for (unsigned i = 0; i < NumVecs; ++i) {  in SelectPostLoadLane()
1350   ReplaceUses(SDValue(N, NumVecs + 1), SDValue(Ld, 2));  in SelectPostLoadLane()
1355 SDNode *AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,  in SelectStoreLane()  argument
1362   SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);  in SelectStoreLane()
1371       cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();  in SelectStoreLane()
1374                    N->getOperand(NumVecs + 3), N->getOperand(0)};  in SelectStoreLane()
1385 SDNode *AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,  in SelectPostStoreLane()  argument
1392   SmallVector<SDValue, 4> Regs(N->op_begin() + 1, N->op_begin() + 1 + NumVecs);  in SelectPostStoreLane()
1404       cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();  in SelectPostStoreLane()
1407                    N->getOperand(NumVecs + 2), // Base Register  in SelectPostStoreLane()
1408                    N->getOperand(NumVecs + 3), // Incremental  in SelectPostStoreLane()