447   setOperationAction(ISD::BITCAST, MVT::i16, Custom);  in AArch64TargetLowering()
448   setOperationAction(ISD::BITCAST, MVT::f16, Custom);  in AArch64TargetLowering()
493   setTargetDAGCombine(ISD::BITCAST);  in AArch64TargetLowering()
2011   Op = DAG.getNode(ISD::BITCAST, DL, MVT::f32, Op);  in LowerBITCAST()
2205                                DAG.getNode(ISD::BITCAST, DL, Op1VT, N00), Op1),  in LowerMUL()
2207                                DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));  in LowerMUL()
2241   case ISD::BITCAST:  in LowerOperation()
2465         ArgValue = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), ArgValue);  in LowerFormalArguments()
2679       Val = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Val);  in LowerCallResult()
3019       Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);  in LowerCall()
3266       Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);  in LowerReturn()
3737       VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);  in LowerFCOPYSIGN()
3738       VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);  in LowerFCOPYSIGN()
3755       VecVal1 = DAG.getNode(ISD::BITCAST, DL, VecVT, In1);  in LowerFCOPYSIGN()
3756       VecVal2 = DAG.getNode(ISD::BITCAST, DL, VecVT, In2);  in LowerFCOPYSIGN()
3767     BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2f64, BuildVec);  in LowerFCOPYSIGN()
3769     BuildVec = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, BuildVec);  in LowerFCOPYSIGN()
3780     return DAG.getNode(ISD::BITCAST, DL, VT, Sel);  in LowerFCOPYSIGN()
3805   Val = DAG.getNode(ISD::BITCAST, DL, MVT::v8i8, Val);  in LowerCTPOP()
4972     Src.ShuffleVec = DAG.getNode(ISD::BITCAST, dl, ShuffleVT, Src.ShuffleVec);  in ReconstructShuffle()
5022   return DAG.getNode(ISD::BITCAST, dl, VT, Shuffle);  in ReconstructShuffle()
5432   SDValue V1Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V1);  in GenerateTBL()
5433   SDValue V2Cst = DAG.getNode(ISD::BITCAST, DL, IndexVT, V2);  in GenerateTBL()
5467   return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Shuffle);  in GenerateTBL()
6274         Ops.push_back(DAG.getNode(ISD::BITCAST, dl, NewType, Op.getOperand(i)));  in LowerBUILD_VECTOR()
6279         return DAG.getNode(ISD::BITCAST, dl, VT, Val);  in LowerBUILD_VECTOR()
6495   while (Op.getOpcode() == ISD::BITCAST)  in getVShiftImm()
7512     SDValue MaskConst = DAG.getNode(ISD::BITCAST, DL, IntVT, SourceConst);  in performVectorCompareAndMaskUnaryOpCombine()
7515     SDValue Res = DAG.getNode(ISD::BITCAST, DL, VT, NewAnd);  in performVectorCompareAndMaskUnaryOpCombine()
7863   if (Op0->getOperand(0)->getOpcode() != ISD::BITCAST)  in performBitcastCombine()
7924                              DAG.getNode(ISD::BITCAST, dl, MidVT, N00),  in performConcatVectorsCombine()
7925                              DAG.getNode(ISD::BITCAST, dl, MidVT, N10), Mask));  in performConcatVectorsCombine()
7952   if (N1->getOpcode() != ISD::BITCAST)  in performConcatVectorsCombine()
7964   return DAG.getNode(ISD::BITCAST, dl, VT,  in performConcatVectorsCombine()
7966                                  DAG.getNode(ISD::BITCAST, dl, RHSTy, N0),  in performConcatVectorsCombine()
8071   return N.getOpcode() == ISD::BITCAST &&  in isEssentiallyExtractSubvector()
9585   Mask = DAG.getNode(ISD::BITCAST, DL,  in performSelectCombine()
9628   case ISD::BITCAST:  in PerformDAGCombine()
9820   Op = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Op);  in ReplaceBITCASTResults()
9843   case ISD::BITCAST:  in ReplaceNodeResults()