5127 static bool isZIPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isZIPMask()  argument
5129   WhichResult = (M[0] == 0 ? 0 : 1);  in isZIPMask()
5130   unsigned Idx = WhichResult * NumElts / 2;  in isZIPMask()
5141 static bool isUZPMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isUZPMask()  argument
5143   WhichResult = (M[0] == 0 ? 0 : 1);  in isUZPMask()
5147     if ((unsigned)M[i] != 2 * i + WhichResult)  in isUZPMask()
5154 static bool isTRNMask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isTRNMask()  argument
5156   WhichResult = (M[0] == 0 ? 0 : 1);  in isTRNMask()
5158     if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||  in isTRNMask()
5159         (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + NumElts + WhichResult))  in isTRNMask()
5168 static bool isZIP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isZIP_v_undef_Mask()  argument
5170   WhichResult = (M[0] == 0 ? 0 : 1);  in isZIP_v_undef_Mask()
5171   unsigned Idx = WhichResult * NumElts / 2;  in isZIP_v_undef_Mask()
5185 static bool isUZP_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isUZP_v_undef_Mask()  argument
5187   WhichResult = (M[0] == 0 ? 0 : 1);  in isUZP_v_undef_Mask()
5189     unsigned Idx = WhichResult;  in isUZP_v_undef_Mask()
5204 static bool isTRN_v_undef_Mask(ArrayRef<int> M, EVT VT, unsigned &WhichResult) {  in isTRN_v_undef_Mask()  argument
5206   WhichResult = (M[0] == 0 ? 0 : 1);  in isTRN_v_undef_Mask()
5208     if ((M[i] >= 0 && (unsigned)M[i] != i + WhichResult) ||  in isTRN_v_undef_Mask()
5209         (M[i + 1] >= 0 && (unsigned)M[i + 1] != i + WhichResult))  in isTRN_v_undef_Mask()
5556   unsigned WhichResult;  in LowerVECTOR_SHUFFLE()  local
5557   if (isZIPMask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5558     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;  in LowerVECTOR_SHUFFLE()
5561   if (isUZPMask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5562     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerVECTOR_SHUFFLE()
5565   if (isTRNMask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5566     unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;  in LowerVECTOR_SHUFFLE()
5570   if (isZIP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5571     unsigned Opc = (WhichResult == 0) ? AArch64ISD::ZIP1 : AArch64ISD::ZIP2;  in LowerVECTOR_SHUFFLE()
5574   if (isUZP_v_undef_Mask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5575     unsigned Opc = (WhichResult == 0) ? AArch64ISD::UZP1 : AArch64ISD::UZP2;  in LowerVECTOR_SHUFFLE()
5578   if (isTRN_v_undef_Mask(ShuffleMask, VT, WhichResult)) {  in LowerVECTOR_SHUFFLE()
5579     unsigned Opc = (WhichResult == 0) ? AArch64ISD::TRN1 : AArch64ISD::TRN2;  in LowerVECTOR_SHUFFLE()