Lines Matching refs:Rd
1227 def : InstAlias<asm # "\t$Rd, $imm, $target",
1228 (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
1275 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1276 [(set regtype:$Rd, (node regtype:$Rn))]>,
1278 bits<5> Rd;
1284 let Inst{4-0} = Rd;
1314 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1315 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1318 bits<5> Rd;
1326 let Inst{4-0} = Rd;
1332 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1337 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1368 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1369 asm, "\t$Rd, $Rn, $Rm", "",
1370 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1371 bits<5> Rd;
1379 let Inst{4-0} = Rd;
1436 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1437 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1438 bits<5> Rd;
1448 let Inst{4-0} = Rd;
1454 [/*(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))*/]>,
1460 [/*(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))*/]>,
1469 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1476 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1477 asm, "\t$Rd, $Rn, $Rm", "",
1478 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1480 bits<5> Rd;
1488 let Inst{4-0} = Rd;
1507 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1508 asm, "\t$Rd, $Rn, $Rm", "",
1509 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1511 bits<5> Rd;
1522 let Inst{4-0} = Rd;
1566 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1567 asm, "\t$Rd, $imm$shift", "", []>,
1569 bits<5> Rd;
1576 let Inst{4-0} = Rd;
1594 : I<(outs regtype:$Rd),
1596 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1598 bits<5> Rd;
1605 let Inst{4-0} = Rd;
1627 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1628 asm, "\t$Rd, $Rn, $imm", "",
1629 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1631 bits<5> Rd;
1640 let Inst{4-0} = Rd;
1646 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1647 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1653 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1654 asm, "\t$Rd, $Rn, $Rm", "",
1655 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1686 bits<5> Rd;
1698 let Inst{4-0} = Rd;
1707 : I<(outs dstRegtype:$Rd),
1709 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1711 bits<5> Rd;
1723 let Inst{4-0} = Rd;
1789 // add Rd, Rb, -imm -> sub Rd, Rn, imm
1790 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1791 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32sp:$Rn,
1793 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1794 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64sp:$Rn,
1864 // Support negative immediates, e.g. adds Rd, Rn, -imm -> subs Rd, Rn, imm
1865 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1866 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32sp:$Rn,
1868 def : InstAlias<alias#"\t$Rd, $Rn, $imm",
1869 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64sp:$Rn,
1928 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1929 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1931 bits<5> Rd;
1941 let Inst{4-0} = Rd;
1946 [(set GPR32:$Rd,
1954 [(set GPR64:$Rd,
1969 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1970 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1972 bits<5> Rd;
1982 let Inst{4-0} = Rd;
2002 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
2004 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
2006 bits<5> Rd;
2016 let Inst{4-0} = Rd;
2041 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
2042 asm, "\t$Rd, $Rn, $imm", "", pattern>,
2044 bits<5> Rd;
2053 let Inst{4-0} = Rd;
2062 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
2063 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
2094 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
2101 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
2106 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2107 (!cast<Instruction>(NAME # "Wri") GPR32sp:$Rd, GPR32:$Rn,
2109 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2110 (!cast<Instruction>(NAME # "Xri") GPR64sp:$Rd, GPR64:$Rn,
2118 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
2123 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
2128 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2129 (!cast<Instruction>(NAME # "Wri") GPR32:$Rd, GPR32:$Rn,
2131 def : InstAlias<Alias # "\t$Rd, $Rn, $imm",
2132 (!cast<Instruction>(NAME # "Xri") GPR64:$Rd, GPR64:$Rn,
2137 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
2138 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
2150 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
2155 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
2174 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
2178 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
2267 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2268 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2269 [(set regtype:$Rd,
2274 bits<5> Rd;
2285 let Inst{4-0} = Rd;
2299 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2300 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2301 [(set regtype:$Rd,
2307 bits<5> Rd;
2318 let Inst{4-0} = Rd;
3532 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3533 asm, "\t$Rd, $Rn", "", pattern>,
3535 bits<5> Rd;
3545 let Inst{4-0} = Rd;
3552 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3553 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3555 bits<5> Rd;
3566 let Inst{4-0} = Rd;
3573 [(set GPR32:$Rd, (OpN FPR16:$Rn))]> {
3580 [(set GPR64:$Rd, (OpN FPR16:$Rn))]> {
3587 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3593 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3599 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3605 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3615 [(set GPR32:$Rd, (OpN (fmul FPR16:$Rn,
3625 [(set GPR64:$Rd, (OpN (fmul FPR16:$Rn,
3634 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3643 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3651 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3660 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3674 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3675 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3677 bits<5> Rd;
3685 let Inst{4-0} = Rd;
3691 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3692 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3694 bits<5> Rd;
3702 let Inst{4-0} = Rd;
3741 [(set FPR16:$Rd,
3751 [(set FPR32:$Rd,
3760 [(set FPR64:$Rd,
3769 [(set FPR16:$Rd,
3778 [(set FPR32:$Rd,
3786 [(set FPR64:$Rd,
3802 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3808 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3810 bits<5> Rd;
3818 let Inst{4-0} = Rd;
3825 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3826 "{\t$Rd"#kind#"$idx, $Rn|"#kind#"\t$Rd$idx, $Rn}", "", []>,
3828 bits<5> Rd;
3836 let Inst{4-0} = Rd;
3845 : I<(outs dstType:$Rd), (ins srcType:$Rn, VectorIndex1:$idx), asm,
3846 "{\t$Rd, $Rn"#kind#"$idx|"#kind#"\t$Rd, $Rn$idx}", "", []>,
3848 bits<5> Rd;
3856 let Inst{4-0} = Rd;
3926 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3928 bits<5> Rd;
3936 let Inst{4-0} = Rd;
3942 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3946 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3950 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3954 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3958 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3962 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3972 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3973 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3975 bits<5> Rd;
3982 let Inst{4-0} = Rd;
4008 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
4009 asm, "\t$Rd, $Rn, $Rm", "", pat>,
4011 bits<5> Rd;
4020 let Inst{4-0} = Rd;
4026 [(set (f16 FPR16:$Rd),
4033 [(set (f32 FPR32:$Rd),
4039 [(set (f64 FPR64:$Rd),
4047 [(set FPR16:$Rd, (fneg (node FPR16:$Rn, (f16 FPR16:$Rm))))]> {
4053 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
4058 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
4070 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
4071 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
4073 bits<5> Rd;
4083 let Inst{4-0} = Rd;
4089 [(set FPR16:$Rd,
4096 [(set FPR32:$Rd,
4102 [(set FPR64:$Rd,
4237 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
4238 asm, "\t$Rd, $Rn, $Rm, $cond", "",
4239 [(set regtype:$Rd,
4243 bits<5> Rd;
4254 let Inst{4-0} = Rd;
4279 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
4280 [(set regtype:$Rd, fpimmtype:$imm)]>,
4282 bits<5> Rd;
4288 let Inst{4-0} = Rd;
4321 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4322 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4323 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
4325 bits<5> Rd;
4337 let Inst{4-0} = Rd;
4344 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
4345 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4346 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4348 bits<5> Rd;
4360 let Inst{4-0} = Rd;
4368 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4371 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4374 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4377 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4380 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4383 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4386 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4394 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
4397 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
4400 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
4403 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
4406 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
4409 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
4417 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4421 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
4425 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4429 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4433 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4437 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4445 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4448 [(set (v16i8 V128:$Rd),
4458 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4461 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4465 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4468 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4471 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4480 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4483 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4487 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4490 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4493 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4502 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn), (v4f16 V64:$Rm)))]>;
4506 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn), (v8f16 V128:$Rm)))]>;
4511 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4515 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4519 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4527 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4530 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4533 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4536 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4544 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4547 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4569 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4573 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4612 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4613 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4614 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4616 bits<5> Rd;
4629 let Inst{4-0} = Rd;
4637 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4638 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4639 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4641 bits<5> Rd;
4654 let Inst{4-0} = Rd;
4662 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4665 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4668 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4671 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4674 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4677 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4683 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4684 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4685 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4687 bits<5> Rd;
4695 let Inst{4-0} = Rd;
4720 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4723 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4726 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4729 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4732 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4735 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4742 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4746 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4750 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4754 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4758 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4762 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4771 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4774 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4777 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4780 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4783 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4786 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4789 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4796 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4799 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4802 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4805 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4808 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4811 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4814 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4823 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4826 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4835 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4838 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4841 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4844 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4854 [(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
4857 [(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
4861 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4864 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4867 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4875 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4878 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4887 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn)))]>;
4890 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn)))]>;
4894 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4897 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4900 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4908 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4911 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4915 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4918 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4921 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4929 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4930 "{\t$Rd" # outkind # ", $Rn" # inkind #
4931 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4933 bits<5> Rd;
4944 let Inst{4-0} = Rd;
4951 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4952 "{\t$Rd" # outkind # ", $Rn" # inkind #
4953 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4955 bits<5> Rd;
4966 let Inst{4-0} = Rd;
4973 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4978 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4983 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4987 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4989 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4990 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4992 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4993 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4995 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5002 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5003 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
5004 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
5005 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
5007 bits<5> Rd;
5020 let Inst{4-0} = Rd;
5102 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
5103 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
5105 bits<5> Rd;
5116 let Inst{4-0} = Rd;
5123 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
5124 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
5126 bits<5> Rd;
5137 let Inst{4-0} = Rd;
5166 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
5170 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
5172 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
5185 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
5186 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
5187 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
5189 bits<5> Rd;
5202 let Inst{4-0} = Rd;
5211 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
5212 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
5213 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
5215 bits<5> Rd;
5228 let Inst{4-0} = Rd;
5240 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
5248 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
5256 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
5265 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
5268 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5270 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
5273 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5275 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
5278 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
5287 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5310 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5314 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5319 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5323 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5332 [(set (v8i16 V128:$Rd),
5337 [(set (v8i16 V128:$Rd),
5343 [(set (v4i32 V128:$Rd),
5348 [(set (v4i32 V128:$Rd),
5354 [(set (v2i64 V128:$Rd),
5359 [(set (v2i64 V128:$Rd),
5371 (add (v8i16 V128:$Rd),
5377 (add (v8i16 V128:$Rd),
5384 (add (v4i32 V128:$Rd),
5390 (add (v4i32 V128:$Rd),
5397 (add (v2i64 V128:$Rd),
5403 (add (v2i64 V128:$Rd),
5413 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5417 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
5422 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5426 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
5431 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5435 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
5446 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
5451 (OpNode (v8i16 V128:$Rd),
5458 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
5463 (OpNode (v4i32 V128:$Rd),
5470 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
5475 (OpNode (v2i64 V128:$Rd),
5486 (Accum (v4i32 V128:$Rd),
5493 (Accum (v4i32 V128:$Rd),
5500 (Accum (v2i64 V128:$Rd),
5507 (Accum (v2i64 V128:$Rd),
5517 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
5521 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
5526 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
5530 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
5535 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5539 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5549 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5550 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5551 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5552 [(set (vty regtype:$Rd),
5555 bits<5> Rd;
5567 let Inst{4-0} = Rd;
5584 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5585 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5586 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5587 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5589 bits<5> Rd;
5602 let Inst{4-0} = Rd;
5642 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5643 "\t$Rd, $Rn, $Rm", "", pattern>,
5645 bits<5> Rd;
5656 let Inst{4-0} = Rd;
5663 : I<oops, iops, asm, "\t$Rd, $Rn, $Rm", "$Rd = $dst", pattern>,
5665 bits<5> Rd;
5677 let Inst{4-0} = Rd;
5683 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5689 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5703 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5710 (ins FPR32:$Rd, FPR32:$Rn, FPR32:$Rm),
5713 (ins FPR16:$Rd, FPR16:$Rn, FPR16:$Rm),
5721 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5723 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5726 [(set FPR16:$Rd, (OpNode FPR16:$Rn, FPR16:$Rm))]>;
5738 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5740 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5754 "\t$Rd, $Rn, $Rm", cstr, pat>,
5756 bits<5> Rd;
5768 let Inst{4-0} = Rd;
5775 (outs FPR32:$Rd),
5778 (outs FPR64:$Rd),
5780 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5788 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5789 asm, "$Rd = $dst", []>;
5792 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5793 asm, "$Rd = $dst",
5795 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5806 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5807 "\t$Rd, $Rn", "", pat>,
5809 bits<5> Rd;
5821 let Inst{4-0} = Rd;
5828 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5829 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5831 bits<5> Rd;
5841 let Inst{4-0} = Rd;
5848 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5849 "\t$Rd, $Rn, #" # zero, "", []>,
5851 bits<5> Rd;
5863 let Inst{4-0} = Rd;
5867 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5868 [(set (f32 FPR32:$Rd), (int_aarch64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5870 bits<5> Rd;
5876 let Inst{4-0} = Rd;
5895 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5896 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn), 0>;
5897 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5898 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn), 0>;
5900 def : InstAlias<asm # "\t$Rd, $Rn, #0",
5901 (!cast<Instruction>(NAME # v1i16rz) FPR16:$Rd, FPR16:$Rn), 0>;
5911 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5928 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5930 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5933 [(set FPR16:$Rd, (OpNode (f16 FPR16:$Rn)))]>;
5941 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5943 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5956 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5958 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5963 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5964 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5973 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5986 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5987 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5989 bits<5> Rd;
5999 let Inst{4-0} = Rd;
6026 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
6027 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
6029 bits<5> Rd;
6040 let Inst{4-0} = Rd;
6075 [(set FPR16:$Rd, (intOp (v4f16 V64:$Rn)))]>;
6078 [(set FPR16:$Rd, (intOp (v8f16 V128:$Rn)))]>;
6082 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
6095 bits<5> Rd;
6104 let Inst{4-0} = Rd;
6109 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
6110 "{\t$Rd" # size # ", $Rn" #
6111 "|" # size # "\t$Rd, $Rn}", "",
6112 [(set (vectype vecreg:$Rd), (AArch64dup regtype:$Rn))]> {
6121 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
6122 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
6123 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
6124 [(set (vectype vecreg:$Rd),
6166 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
6167 "{\t$Rd, $Rn" # size # "$idx" #
6168 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
6178 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
6246 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
6247 "{\t$Rd" # size # "$idx, $Rn" #
6248 "|" # size # "\t$Rd$idx, $Rn}",
6249 "$Rd = $dst",
6251 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
6258 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
6259 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
6260 "|" # size # "\t$Rd$idx, $Rn$idx2}",
6261 "$Rd = $dst",
6264 (vectype V128:$Rd),
6571 bits<5> Rd;
6581 let Inst{4-0} = Rd;
6588 : BaseSIMDModifiedImm<Q, op, op2, (outs vectype:$Rd),
6590 "{\t$Rd" # kind # ", $imm8" # opt_shift #
6591 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6601 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
6602 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
6603 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
6604 "$Rd = $dst", pattern> {
6677 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6682 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6688 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6693 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6720 : BaseSIMDModifiedImm<Q, op, 0, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6721 "\t$Rd, $imm8", "", pattern> {
6736 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6738 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6739 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6741 bits<5> Rd;
6757 let Inst{4-0} = Rd;
6767 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6768 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6769 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6771 bits<5> Rd;
6787 let Inst{4-0} = Rd;
6797 [(set (v4f16 V64:$Rd),
6810 [(set (v8f16 V128:$Rd),
6824 [(set (v2f32 V64:$Rd),
6836 [(set (v4f32 V128:$Rd),
6848 [(set (v2f64 V128:$Rd),
6860 [(set (f16 FPR16Op:$Rd),
6874 [(set (f32 FPR32Op:$Rd),
6886 [(set (f64 FPR64Op:$Rd),
6898 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6902 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6903 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6905 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6910 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6914 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6915 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6917 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6921 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6925 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6926 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6928 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6932 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6934 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6936 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6938 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6942 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6944 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
7029 [(set (v4i16 V64:$Rd),
7042 [(set (v8i16 V128:$Rd),
7055 [(set (v2i32 V64:$Rd),
7067 [(set (v4i32 V128:$Rd),
7087 [(set (i32 FPR32Op:$Rd),
7103 [(set (v4i16 V64:$Rd),
7116 [(set (v8i16 V128:$Rd),
7129 [(set (v2i32 V64:$Rd),
7141 [(set (v4i32 V128:$Rd),
7156 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
7169 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7182 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7194 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7208 [(set (v4i32 V128:$Rd),
7221 [(set (v4i32 V128:$Rd),
7236 [(set (v2i64 V128:$Rd),
7248 [(set (v2i64 V128:$Rd),
7282 (Accum (v4i32 V128:$Rd),
7295 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
7303 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
7312 (Accum (v4i32 V128:$Rd),
7329 (Accum (v2i64 V128:$Rd),
7344 (Accum (v2i64 V128:$Rd),
7369 (Accum (i64 FPR64Op:$Rd),
7388 [(set (v4i32 V128:$Rd),
7401 [(set (v4i32 V128:$Rd),
7416 [(set (v2i64 V128:$Rd),
7428 [(set (v2i64 V128:$Rd),
7447 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
7460 (OpNode (v4i32 V128:$Rd),
7475 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
7487 (OpNode (v2i64 V128:$Rd),
7506 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
7507 asm, "\t$Rd, $Rn, $imm", "", pattern>,
7509 bits<5> Rd;
7519 let Inst{4-0} = Rd;
7526 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
7527 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
7529 bits<5> Rd;
7539 let Inst{4-0} = Rd;
7565 [(set (i64 FPR64:$Rd),
7578 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
7583 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
7585 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
7593 [(set (v1i64 FPR64:$Rd),
7622 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
7641 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
7647 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
7687 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7688 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7689 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7691 bits<5> Rd;
7701 let Inst{4-0} = Rd;
7710 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7711 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7712 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7714 bits<5> Rd;
7724 let Inst{4-0} = Rd;
7733 [(set (v4i16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (i32 imm:$imm)))]> {
7741 [(set (v8i16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (i32 imm:$imm)))]> {
7749 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7757 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7765 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7777 [(set (v4f16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (i32 imm:$imm)))]> {
7785 [(set (v8f16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (i32 imm:$imm)))]> {
7794 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7802 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7810 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7821 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7837 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7853 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7871 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7874 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7876 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7879 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7881 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7884 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7893 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7902 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7911 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7920 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7929 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7938 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7947 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7959 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7968 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7977 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7986 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7995 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
8004 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
8013 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
8026 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
8035 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
8044 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
8053 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
8062 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
8071 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8080 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
8093 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
8103 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
8113 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
8123 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
8133 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
8143 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8153 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
8164 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
8172 [(set (v8i16 V128:$Rd),
8180 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
8188 [(set (v4i32 V128:$Rd),
8197 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
8205 [(set (v2i64 V128:$Rd),
9078 (Accum (v4i16 V64:$Rd),
9083 (Accum (v8i16 V128:$Rd),
9088 (Accum (v2i32 V64:$Rd),
9093 (Accum (v4i32 V128:$Rd),
9104 (Accum (v4i16 V64:$Rd),
9119 (Accum (v8i16 V128:$Rd),
9134 (Accum (v2i32 V64:$Rd),
9148 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
9162 FPR32Op:$Rd,
9173 (Accum (v4i32 V128:$Rd),
9185 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
9196 FPR32Op:$Rd,
9217 (Accum (i32 FPR32Op:$Rd),
9237 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
9239 bits<5> Rd;
9245 let Inst{4-0} = Rd;
9249 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
9250 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
9253 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
9254 "$Rd = $dst",
9256 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
9262 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
9263 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
9265 bits<5> Rd;
9274 let Inst{4-0} = Rd;
9279 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
9281 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
9286 (ins V128:$Rd, V128:$Rn, V128:$Rm),
9288 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
9293 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
9295 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
9302 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
9303 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
9305 bits<5> Rd;
9311 let Inst{4-0} = Rd;
9315 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
9316 (ins V128:$Rd, V128:$Rn),
9318 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
9321 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
9322 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;