Lines Matching refs:Opc
304 unsigned Opc = 0; in canFoldIntoCSel() local
320 Opc = Is64Bit ? AArch64::CSINCXr : AArch64::CSINCWr; in canFoldIntoCSel()
330 Opc = Is64Bit ? AArch64::CSINVXr : AArch64::CSINVWr; in canFoldIntoCSel()
347 Opc = Is64Bit ? AArch64::CSNEGXr : AArch64::CSNEGWr; in canFoldIntoCSel()
353 assert(Opc && SrcOpNum && "Missing parameters"); in canFoldIntoCSel()
357 return Opc; in canFoldIntoCSel()
485 unsigned Opc = 0; in insertSelect() local
490 Opc = AArch64::CSELXr; in insertSelect()
494 Opc = AArch64::CSELWr; in insertSelect()
498 Opc = AArch64::FCSELDrrr; in insertSelect()
501 Opc = AArch64::FCSELSrrr; in insertSelect()
520 Opc = FoldedOpc; in insertSelect()
531 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm( in insertSelect()
839 unsigned Opc = CmpInstr->getOpcode(); in optimizeCompareInstr() local
841 if (NewOpc == Opc) in optimizeCompareInstr()
928 unsigned Opc = Instr.getOpcode(); in optimizeCompareInstr() local
930 switch (Opc) { in optimizeCompareInstr()
1845 unsigned Opc = 0; in storeRegToStackSlot() local
1850 Opc = AArch64::STRBui; in storeRegToStackSlot()
1854 Opc = AArch64::STRHui; in storeRegToStackSlot()
1858 Opc = AArch64::STRWui; in storeRegToStackSlot()
1864 Opc = AArch64::STRSui; in storeRegToStackSlot()
1868 Opc = AArch64::STRXui; in storeRegToStackSlot()
1874 Opc = AArch64::STRDui; in storeRegToStackSlot()
1878 Opc = AArch64::STRQui; in storeRegToStackSlot()
1882 Opc = AArch64::ST1Twov1d, Offset = false; in storeRegToStackSlot()
1889 Opc = AArch64::ST1Threev1d, Offset = false; in storeRegToStackSlot()
1896 Opc = AArch64::ST1Fourv1d, Offset = false; in storeRegToStackSlot()
1900 Opc = AArch64::ST1Twov2d, Offset = false; in storeRegToStackSlot()
1907 Opc = AArch64::ST1Threev2d, Offset = false; in storeRegToStackSlot()
1914 Opc = AArch64::ST1Fourv2d, Offset = false; in storeRegToStackSlot()
1918 assert(Opc && "Unknown register class"); in storeRegToStackSlot()
1920 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) in storeRegToStackSlot()
1943 unsigned Opc = 0; in loadRegFromStackSlot() local
1948 Opc = AArch64::LDRBui; in loadRegFromStackSlot()
1952 Opc = AArch64::LDRHui; in loadRegFromStackSlot()
1956 Opc = AArch64::LDRWui; in loadRegFromStackSlot()
1962 Opc = AArch64::LDRSui; in loadRegFromStackSlot()
1966 Opc = AArch64::LDRXui; in loadRegFromStackSlot()
1972 Opc = AArch64::LDRDui; in loadRegFromStackSlot()
1976 Opc = AArch64::LDRQui; in loadRegFromStackSlot()
1980 Opc = AArch64::LD1Twov1d, Offset = false; in loadRegFromStackSlot()
1987 Opc = AArch64::LD1Threev1d, Offset = false; in loadRegFromStackSlot()
1994 Opc = AArch64::LD1Fourv1d, Offset = false; in loadRegFromStackSlot()
1998 Opc = AArch64::LD1Twov2d, Offset = false; in loadRegFromStackSlot()
2005 Opc = AArch64::LD1Threev2d, Offset = false; in loadRegFromStackSlot()
2012 Opc = AArch64::LD1Fourv2d, Offset = false; in loadRegFromStackSlot()
2016 assert(Opc && "Unknown register class"); in loadRegFromStackSlot()
2018 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc)) in loadRegFromStackSlot()
2049 unsigned Opc; in emitFrameOffset() local
2051 Opc = isSub ? AArch64::SUBSXri : AArch64::ADDSXri; in emitFrameOffset()
2053 Opc = isSub ? AArch64::SUBXri : AArch64::ADDXri; in emitFrameOffset()
2066 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) in emitFrameOffset()
2077 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg) in emitFrameOffset()
2403 static bool isCombineInstrSettingFlag(unsigned Opc) { in isCombineInstrSettingFlag() argument
2404 switch (Opc) { in isCombineInstrSettingFlag()
2422 static bool isCombineInstrCandidate32(unsigned Opc) { in isCombineInstrCandidate32() argument
2423 switch (Opc) { in isCombineInstrCandidate32()
2441 static bool isCombineInstrCandidate64(unsigned Opc) { in isCombineInstrCandidate64() argument
2442 switch (Opc) { in isCombineInstrCandidate64()
2460 static bool isCombineInstrCandidate(unsigned Opc) { in isCombineInstrCandidate() argument
2461 return (isCombineInstrCandidate32(Opc) || isCombineInstrCandidate64(Opc)); in isCombineInstrCandidate()
2499 unsigned Opc = Root.getOpcode(); in getMachineCombinerPatterns() local
2503 if (!isCombineInstrCandidate(Opc)) in getMachineCombinerPatterns()
2505 if (isCombineInstrSettingFlag(Opc)) { in getMachineCombinerPatterns()
2513 if (NewOpc == Opc) in getMachineCombinerPatterns()
2515 Opc = NewOpc; in getMachineCombinerPatterns()
2518 switch (Opc) { in getMachineCombinerPatterns()
2713 unsigned Opc; in genAlternativeCodeSequence() local
2725 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
2728 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
2731 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 1, Opc, RC); in genAlternativeCodeSequence()
2740 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
2743 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
2746 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); in genAlternativeCodeSequence()
2762 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
2769 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
2788 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); in genAlternativeCodeSequence()
2805 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
2811 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
2822 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); in genAlternativeCodeSequence()
2832 Opc = AArch64::MSUBWrrr; in genAlternativeCodeSequence()
2835 Opc = AArch64::MSUBXrrr; in genAlternativeCodeSequence()
2838 MUL = genMadd(MF, MRI, TII, Root, InsInstrs, 2, Opc, RC); in genAlternativeCodeSequence()
2854 Opc = AArch64::MADDWrrr; in genAlternativeCodeSequence()
2861 Opc = AArch64::MADDXrrr; in genAlternativeCodeSequence()
2879 MUL = genMaddR(MF, MRI, TII, Root, InsInstrs, 1, Opc, NewVR, RC); in genAlternativeCodeSequence()