Lines Matching refs:constrainRegClass
442 MRI.constrainRegClass(SrcReg, &AArch64::GPR64spRegClass); in insertSelect()
448 MRI.constrainRegClass(SrcReg, &AArch64::GPR32spRegClass); in insertSelect()
488 if (MRI.constrainRegClass(DstReg, &AArch64::GPR64RegClass)) { in insertSelect()
492 } else if (MRI.constrainRegClass(DstReg, &AArch64::GPR32RegClass)) { in insertSelect()
496 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR64RegClass)) { in insertSelect()
499 } else if (MRI.constrainRegClass(DstReg, &AArch64::FPR32RegClass)) { in insertSelect()
527 MRI.constrainRegClass(TrueReg, RC); in insertSelect()
528 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
737 !MRI->constrainRegClass(Reg, OpRegCstraints)) in UpdateOperandRegClass()
1860 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR32RegClass); in storeRegToStackSlot()
1870 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in storeRegToStackSlot()
1958 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR32RegClass); in loadRegFromStackSlot()
1968 MF.getRegInfo().constrainRegClass(DestReg, &AArch64::GPR64RegClass); in loadRegFromStackSlot()
2105 MF.getRegInfo().constrainRegClass(DstReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
2110 MF.getRegInfo().constrainRegClass(SrcReg, &AArch64::GPR64RegClass); in foldMemoryOperandImpl()
2632 MRI.constrainRegClass(ResultReg, RC); in genMadd()
2634 MRI.constrainRegClass(SrcReg0, RC); in genMadd()
2636 MRI.constrainRegClass(SrcReg1, RC); in genMadd()
2638 MRI.constrainRegClass(SrcReg2, RC); in genMadd()
2680 MRI.constrainRegClass(ResultReg, RC); in genMaddR()
2682 MRI.constrainRegClass(SrcReg0, RC); in genMaddR()
2684 MRI.constrainRegClass(SrcReg1, RC); in genMaddR()
2686 MRI.constrainRegClass(VR, RC); in genMaddR()