Lines Matching refs:LD1
1367 // We must do vector loads with LD1 in big-endian.
1380 // We must do vector loads with LD1 in big-endian.
1507 // We must use LD1 to perform vector loads in big-endian.
1526 // We must use LD1 to perform vector loads in big-endian.
4938 defm LD1 : SIMDLd1Multiple<"ld1">;
4982 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4983 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4984 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4985 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
5031 ValueType VTy, ValueType STy, Instruction LD1>
5034 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
5045 ValueType VTy, ValueType STy, Instruction LD1>
5049 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
5060 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
5292 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
5295 // to use LD1/ST1 only to simplify compiler implementation.
5297 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes