Lines Matching refs:TM

184   AArch64PassConfig(AArch64TargetMachine *TM, PassManagerBase &PM)  in AArch64PassConfig()  argument
185 : TargetPassConfig(TM, PM) { in AArch64PassConfig()
186 if (TM->getOptLevel() != CodeGenOpt::None) in AArch64PassConfig()
218 addPass(createAtomicExpandPass(TM)); in addIRPasses()
223 if (TM->getOptLevel() != CodeGenOpt::None && EnableAtomicTidy) in addIRPasses()
229 if (TM->getOptLevel() != CodeGenOpt::None) in addIRPasses()
230 addPass(createInterleavedAccessPass(TM)); in addIRPasses()
232 if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) { in addIRPasses()
236 addPass(createSeparateConstOffsetFromGEPPass(TM, true)); in addIRPasses()
250 if (TM->getOptLevel() != CodeGenOpt::None && EnablePromoteConstant) in addPreISel()
255 if ((TM->getOptLevel() != CodeGenOpt::None && in addPreISel()
258 bool OnlyOptimizeForSize = (TM->getOptLevel() < CodeGenOpt::Aggressive) && in addPreISel()
260 addPass(createGlobalMergePass(TM, 4095, OnlyOptimizeForSize)); in addPreISel()
263 if (TM->getOptLevel() != CodeGenOpt::None) in addPreISel()
274 if (TM->getTargetTriple().isOSBinFormatELF() && in addInstSelector()
297 if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) { in addPreRegAlloc()
307 if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination) in addPostRegAlloc()
309 if (TM->getOptLevel() != CodeGenOpt::None && usingDefaultRegAlloc()) in addPostRegAlloc()
318 if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt) in addPreSched2()
328 if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH && in addPreEmitPass()
329 TM->getTargetTriple().isOSBinFormatMachO()) in addPreEmitPass()