47 EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {  in getEquivalentMemType()
57 EVT AMDGPUTargetLowering::getEquivalentLoadRegType(LLVMContext &Ctx, EVT VT) {  in getEquivalentLoadRegType()
65 AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM,  in AMDGPUTargetLowering()  function in AMDGPUTargetLowering
417 MVT AMDGPUTargetLowering::getVectorIdxTy(const DataLayout &) const {  in getVectorIdxTy()
421 bool AMDGPUTargetLowering::isSelectSupported(SelectSupportKind SelType) const {  in isSelectSupported()
427 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {  in isFPImmLegal()
433 bool AMDGPUTargetLowering::ShouldShrinkFPConstant(EVT VT) const {  in ShouldShrinkFPConstant()
438 bool AMDGPUTargetLowering::shouldReduceLoadWidth(SDNode *N,  in shouldReduceLoadWidth()
461 bool AMDGPUTargetLowering::isLoadBitCastBeneficial(EVT LoadTy,  in isLoadBitCastBeneficial()
478 bool AMDGPUTargetLowering::isCheapToSpeculateCttz() const {  in isCheapToSpeculateCttz()
482 bool AMDGPUTargetLowering::isCheapToSpeculateCtlz() const {  in isCheapToSpeculateCtlz()
490 bool AMDGPUTargetLowering::isFAbsFree(EVT VT) const {  in isFAbsFree()
495 bool AMDGPUTargetLowering::isFNegFree(EVT VT) const {  in isFNegFree()
500 bool AMDGPUTargetLowering:: storeOfVectorConstantIsCheap(EVT MemVT,  in storeOfVectorConstantIsCheap()
506 bool AMDGPUTargetLowering::aggressivelyPreferBuildVectorSources(EVT VecVT) const {  in aggressivelyPreferBuildVectorSources()
518 bool AMDGPUTargetLowering::isTruncateFree(EVT Source, EVT Dest) const {  in isTruncateFree()
523 bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {  in isTruncateFree()
529 bool AMDGPUTargetLowering::isZExtFree(Type *Src, Type *Dest) const {  in isZExtFree()
536 bool AMDGPUTargetLowering::isZExtFree(EVT Src, EVT Dest) const {  in isZExtFree()
544 bool AMDGPUTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {  in isZExtFree()
548 bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {  in isNarrowingProfitable()
562 void AMDGPUTargetLowering::AnalyzeFormalArguments(CCState &State,  in AnalyzeFormalArguments()
568 SDValue AMDGPUTargetLowering::LowerReturn(  in LowerReturn()
582 SDValue AMDGPUTargetLowering::LowerCall(CallLoweringInfo &CLI,  in LowerCall()
601 SDValue AMDGPUTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,  in LowerDYNAMIC_STACKALLOC()
610 SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op,  in LowerOperation()
641 void AMDGPUTargetLowering::ReplaceNodeResults(SDNode *N,  in ReplaceNodeResults()
686 SDValue AMDGPUTargetLowering::LowerConstantInitializer(const Constant* Init,  in LowerConstantInitializer()
775 SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,  in LowerGlobalAddress()
855 SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,  in LowerCONCAT_VECTORS()
865 SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,  in LowerEXTRACT_SUBVECTOR()
877 SDValue AMDGPUTargetLowering::LowerFrameIndex(SDValue Op,  in LowerFrameIndex()
893 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,  in LowerINTRINSIC_WO_CHAIN()
1056 SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,  in LowerIntrinsicIABS()
1068 SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,  in LowerIntrinsicLRP()
1084 SDValue AMDGPUTargetLowering::CombineFMinMaxLegacy(SDLoc DL,  in CombineFMinMaxLegacy()
1163 SDValue AMDGPUTargetLowering::ScalarizeVectorLoad(const SDValue Op,  in ScalarizeVectorLoad()
1203 SDValue AMDGPUTargetLowering::SplitVectorLoad(const SDValue Op,  in SplitVectorLoad()
1258 SDValue AMDGPUTargetLowering::MergeVectorStore(const SDValue &Op,  in MergeVectorStore()
1316 SDValue AMDGPUTargetLowering::ScalarizeVectorStore(SDValue Op,  in ScalarizeVectorStore()
1348 SDValue AMDGPUTargetLowering::SplitVectorStore(SDValue Op,  in SplitVectorStore()
1403 SDValue AMDGPUTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {  in LowerLOAD()
1483 SDValue AMDGPUTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {  in LowerSTORE()
1485   SDValue Result = AMDGPUTargetLowering::MergeVectorStore(Op, DAG);  in LowerSTORE()
1546 SDValue AMDGPUTargetLowering::LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const {  in LowerDIVREM24()
1645 void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,  in LowerUDIVREM64()
1720 SDValue AMDGPUTargetLowering::LowerUDIVREM(SDValue Op,  in LowerUDIVREM()
1840 SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,  in LowerSDIVREM()
1901 SDValue AMDGPUTargetLowering::LowerFREM(SDValue Op, SelectionDAG &DAG) const {  in LowerFREM()
1916 SDValue AMDGPUTargetLowering::LowerFCEIL(SDValue Op, SelectionDAG &DAG) const {  in LowerFCEIL()
1955 SDValue AMDGPUTargetLowering::LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const {  in LowerFTRUNC()
2005 SDValue AMDGPUTargetLowering::LowerFRINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFRINT()
2032 SDValue AMDGPUTargetLowering::LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const {  in LowerFNEARBYINT()
2040 SDValue AMDGPUTargetLowering::LowerFROUND32(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND32()
2068 SDValue AMDGPUTargetLowering::LowerFROUND64(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND64()
2125 SDValue AMDGPUTargetLowering::LowerFROUND(SDValue Op, SelectionDAG &DAG) const {  in LowerFROUND()
2137 SDValue AMDGPUTargetLowering::LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const {  in LowerFFLOOR()
2162 SDValue AMDGPUTargetLowering::LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG,  in LowerINT_TO_FP64()
2185 SDValue AMDGPUTargetLowering::LowerUINT_TO_FP(SDValue Op,  in LowerUINT_TO_FP()
2212 SDValue AMDGPUTargetLowering::LowerSINT_TO_FP(SDValue Op,  in LowerSINT_TO_FP()
2221 SDValue AMDGPUTargetLowering::LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG,  in LowerFP64_TO_INT()
2250 SDValue AMDGPUTargetLowering::LowerFP_TO_SINT(SDValue Op,  in LowerFP_TO_SINT()
2260 SDValue AMDGPUTargetLowering::LowerFP_TO_UINT(SDValue Op,  in LowerFP_TO_UINT()
2270 SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,  in LowerSIGN_EXTEND_INREG()
2354 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,  in performStoreCombine()
2392 SDValue AMDGPUTargetLowering::performShlCombine(SDNode *N,  in performShlCombine()
2419 SDValue AMDGPUTargetLowering::performMulCombine(SDNode *N,  in performMulCombine()
2450 SDValue AMDGPUTargetLowering::PerformDAGCombine(SDNode *N,  in PerformDAGCombine()
2586 void AMDGPUTargetLowering::getOriginalFunctionArgs(  in getOriginalFunctionArgs()
2618 bool AMDGPUTargetLowering::isHWTrueValue(SDValue Op) const {  in isHWTrueValue()
2625 bool AMDGPUTargetLowering::isHWFalseValue(SDValue Op) const {  in isHWFalseValue()
2632 SDValue AMDGPUTargetLowering::CreateLiveInRegister(SelectionDAG &DAG,  in CreateLiveInRegister()
2647 uint32_t AMDGPUTargetLowering::getImplicitParameterOffset(  in getImplicitParameterOffset()
2661 const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {  in getTargetNodeName()
2735 SDValue AMDGPUTargetLowering::getRsqrtEstimate(SDValue Operand,  in getRsqrtEstimate()
2753 SDValue AMDGPUTargetLowering::getRecipEstimate(SDValue Operand,  in getRecipEstimate()
2790 void AMDGPUTargetLowering::computeKnownBitsForTargetNode(  in computeKnownBitsForTargetNode()
2845 unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(  in ComputeNumSignBitsForTargetNode()